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orner number i14030 L64724 satellite receiver technical manual april 2000 L64724tm_300.book page i friday, april 14, 2000 2:17 pm
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?cer of lsi logic corporation. document db14-000032-03, april 2000 this document describes release b of lsi logic corporations L64724 satellite receiver and will remain the of?cial reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright ? 2000 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design and g10 are registered trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. L64724tm_300.book page ii friday, april 14, 2000 2:17 pm
contents iii contents chapter 1 introduction 1.1 general description 1-1 1.2 typical application 1-3 1.3 features summary 1-5 chapter 2 L64724 signal de?nitions 2.1 channel interface 2-3 2.2 channel clock interface 2-4 2.3 phase-locked loop (pll) interface 2-4 2.4 control signals interface 2-5 2.5 agc/clock control interface 2-6 2.6 channel data output interface 2-6 2.7 analog-to-digital converter (adc) interface 2-7 2.8 microcontroller interfaceea 2-8 chapter 3 L64724 registers 3.1 L64724 register overview 3-1 3.2 reset and how it affects registers 3-7 3.3 groups 0 and 1: address pointer register 3-8 3.4 group 2: system mode and system status registers 3-9 3.5 group 3: status registers 3-23 3.6 group 4: con?guration registers 3-33 3.7 group 5: self-tuning microcontroller registers 3-77 3.8 group 6: reserved (internal use only) 3-81 3.9 group 7: arbiter control register 3-81 3.10 reset effect on register bits 3-82 3.11 internal data path reset effects 3-84 L64724tm_300.book page iii friday, april 14, 2000 2:17 pm
iv contents chapter 4 channel interfaces and data control 4.1 data control and clocking schemes 4-2 4.2 pll clock generation 4-3 4.3 data path input interface 4-12 4.4 data output interface 4-14 chapter 5 demodulator module functional description 5.1 overview 5-2 5.2 analog to digital conversion 5-2 5.3 dc offset compensation and coupling to adc output 5-3 5.4 decimation filters 5-4 5.5 matched filter 5-7 5.6 timing clock recovery 5-8 5.7 carrier recovery loop 5-12 5.8 automatic gain control (agc) 5-20 5.9 output control 5-22 5.10 external controls 5-23 chapter 6 decoding pipeline synchronization 6.1 synchronization scheme 6-1 6.2 viterbi decoder synchronization 6-2 6.3 reed-solomon deinterleaver synchronization 6-8 6.4 descrambler synchronization 6-13 chapter 7 the fec decoder pipeline 7.1 viterbi decoder module 7-1 7.2 deinterleaver module 7-8 7.3 reed-solomon decoder 7-10 7.4 descrambler module architecture and operation 7-15 7.5 fec module software reset 7-17 chapter 8 L64724 speci?cations 8.1 electrical requirements 8-1 8.2 ac timing 8-6 8.3 L64724 packaging 8-15 L64724tm_300.book page iv friday, april 14, 2000 2:17 pm
contents v appendix a programming the L64724 using the serial bus protocol a.1 serial bus protocol overview a-2 a.2 programming the slave address using the serial bus interface a-4 a.3 write cycle using the serial bus interface a-4 a.4 read cycle using the serial bus interface a-7 appendix b L64724 application notes b.1 L64724 qpsk demodulator acquisition and debugging tips b-1 b.2 demodulator con?guration tips b-5 b.3 qpsk demodulator and fec con?guration example: high data rates b-10 b.4 qpsk demodulator and fec con?guration example: low data rates b-30 appendix c programming the serializer c.1 serializer overview c-1 c.2 serializer interface signals and con?guration registers c-2 c.3 programming for serial mode (2-wire compliant) c-4 c.4 programming for 3-wire mode c-6 appendix d a/d converters d.1 adc overview d-2 d.2 board level interface d-2 d.3 dc characteristics d-5 d.4 ac characteristics d-5 appendix e L64724 on-chip microcontroller e.1 L64724 microcontroller instruction set e-2 e.2 microcontroller address map e-5 customer feedback L64724tm_300.book page v friday, april 14, 2000 2:17 pm
vi contents figures 1.1 L64724 block diagram 1-2 1.2 set-top decoder box block diagram 1-4 2.1 L64724 logic symbol 2-2 3.1 register file structure 3-3 3.2 issue a hard reset 3-5 3.3 initialize apr0 and apr1 to zero 3-5 3.4 write locations 0 and 1 in group 4 3-6 3.5 read back group 4 3-6 4.1 L64724 clocking: internal pll 4-2 4.2 pll clock synthesis 4-4 4.3 L64724 functional blocks in the decoding pipeline 4-12 4.4 clk and analog inputs for channel data input 4-13 4.5 clk and digital inputs for adc bypass mode 4-13 4.6 parallel output interface waveforms 4-15 4.7 descrambler parallel output waveforms 4-16 4.8 descrambler serial output waveforms 4-17 5.1 demodulator module and associated circuitry 5-2 5.2 input quantization 5-3 5.3 clock recovery loop 5-8 5.4 timing loop sweep operation 5-11 5.5 carrier recovery loop 5-12 5.6 frequency sweeping 5-13 5.7 snr threshold vs. e s /n o 5-17 5.8 carrier loop filter parameters 5-17 5.9 eye pattern and adc range 5-20 5.10 agc loop control 5-22 6.1 synchronization module 6-2 6.2 viterbi decoder synchronization 6-3 6.3 phase rotation for synchronization 6-4 6.4 channel symbol error rate vs. snr for rate = 1/2 code 6-5 6.5 channel symbol error rate vs. snr for rate = 2/3 code 6-5 6.6 channel symbol error rate vs. snr for rate = 3/4 code 6-6 6.7 channel symbol error rate vs. snr for rate = 5/6 code 6-6 6.8 channel symbol error rate vs. snr for rate = 6/7 code 6-7 6.9 channel symbol error rate vs. snr for rate = 7/8 code 6-7 6.10 reed-solomon, deinterleaver synchronization 6-8 L64724tm_300.book page vi friday, april 14, 2000 2:17 pm
contents vii 6.11 synchronization, tracking, and loss of sync for three missed sync words 6-9 6.12 minimum and maximum number of states in the acquisition phase 6-10 6.13 minimum and maximum number of states in the tracking phase 6-11 6.14 dss packet 6-12 6.15 mpeg-2 transport packet 6-12 6.16 L64724 transport packet 6-12 6.17 descrambler synchronization 6-13 7.1 viterbi decoder block diagram 7-2 7.2 puncturing and depuncturing block diagram 7-4 7.3 puncture pattern for different code rates 7-5 7.4 block diagram of viterbi bit error detection circuit 7-7 7.5 interleaving/deinterleaving operation for dvb 7-8 7.6 interleaving/deinterleaving operation for dss 7-9 7.7 code word structure 7-12 7.8 fec data path 7-12 7.9 122-bit burst example 7-14 7.10 descrambler block diagram 7-16 7.11 15-bit shift register initialization 7-16 7.12 inverted sync words in descrambler 7-17 8.1 ac test load and waveform for standard outputs 8-6 8.2 ac test load and waveforms for 3-state outputs 8-6 8.3 L64724 synchronous ac timing 8-7 8.4 L64724 reset timing diagram 8-7 8.5 L64724 bus 3-state delay timing 8-7 8.6 L64724 decoder read cycle 8-8 8.7 L64724 decoder write cycle 8-8 8.8 100-pin pqfp/mqfp pinout 8-16 8.9 100-pin pqfp/mqfp mechanical drawing 8-17 8.9 100-pin pqfp/mqfp mechanical drawing (cont.) 8-18 a.1 serial bus architecture a-2 a.2 7-bit slave address for the L64724 serial bus a-2 a.3 serial bus write/read cycle overview a-3 a.4 general call structure a-4 a.5 burst write or single write to slave (master-transmitter, slave-receiver) a-6 L64724tm_300.book page vii friday, april 14, 2000 2:17 pm
viii contents a.6 burst read or single read cycle from slave a-8 b.1 agc loop control b-3 c.1 2-wire compliant interface c-5 c.2 3-wire interface c-7 c.3 28-bit write using 3-wire mode c-8 d.1 adc connections for L64724 d-2 d.2 adc board level interface d-3 e.1 registers shared between the host up and L64724 mc e-2 tables 3.1 register overview 3-2 3.2 group 2 system mode register map (write-only) 3-10 3.3 group 2 system status register map (read-only) 3-17 3.4 group 3 register map 3-23 3.5 group 4 register map 3-34 3.6 group 5 register map 3-77 3.7 reset map 3-83 4.1 parameters for crystal clock (clk) = 15 mhz 4-5 4.2 parameters for crystal clock (clk) = 4 mhz 4-8 4.3 input con?guration 4-13 4.4 output selection 4-14 5.1 decimation procedure 5-4 5.2 decimation results 5-5 5.3 roll-off factor 5-7 5.4 ped gain for carrier loop 5-19 5.5 pwr_bw as a function of symbol rate 5-21 7.1 puncture patterns for various code rates 7-3 8.1 L64724 absolute maximum rating (referenced to v ss ) 8-2 8.2 L64724 recommended operating conditions 8-2 8.3 L64724 capacitance 8-2 8.4 dc characteristics of the L64724 8-3 8.5 L64724 pin description summary 8-4 8.6 L64724-75 ac timing parameters with microcontroller disabled 8-9 8.7 L64724-75 ac timing parameters with microcontroller enabled 8-11 8.8 L64724-90 ac timing parameters with microcontroller disabled 8-12 8.9 L64724-90 ac timing parameters with microcontroller enabled 8-14 L64724tm_300.book page viii friday, april 14, 2000 2:17 pm
contents ix 8.10 L64724 ordering information 8-15 b.1 pwr_lvl register setting b-3 b.2 decimation procedure b-7 b.3 decimation results b-7 b.4 carrier loop control 1 register bits b-19 b.5 clock loop con?guration register bits b-22 b.6 demodulator con?guration register bits b-23 b.7 external output control bits and reset register bits b-23 b.8 high data rate register values b-26 b.9 carrier loop con?guration register bits b-38 b.10 clock loop con?guration register bits b-42 b.11 demodulator con?guration register bits b-43 b.12 external output control bits and reset register bits b-43 b.13 group 4, apr 62 register bits b-44 b.14 low data rate register values b-45 d.1 dc characteristics d-5 d.2 ac characteristics d-5 e.1 L64724 mc instruction set e-2 e.2 microcontroller address map e-5 L64724tm_300.book page ix friday, april 14, 2000 2:17 pm
x contents L64724tm_300.book page x friday, april 14, 2000 2:17 pm
preface xi preface this manual is the primary reference and technical manual for the L64724 satellite receiver. it contains a complete functional description for the L64724 and includes complete physical and electrical speci?cations. audience this document assumes that you have some familiarity with digital satellite communications, microprocessors, and related support devices. the people who bene?t from this book are: engineers and managers who are evaluating the L64724 for possible use in a digital satellite receiver engineers who are designing the L64724 into a digital satellite receiver organization this document has the following chapters and appendices: chapter 1, introduction , de?nes the general characteristics and capabilities of the L64724 satellite receiver. chapter 2, L64724 signal de?nitions , describes the characteristics of the L64724 signals that are used to interface with an external channel and microcontroller. chapter 3, L64724 registers , provides a summary of the registers in the L64724. chapter 4, channel interfaces and data control , discusses the input channel and output channel interfaces and the circuitry that supports them. L64724tm_300.book page xi friday, april 14, 2000 2:17 pm
xii preface chapter 5, demodulator module functional description , describes the operation of the demodulator portion of the satellite receiver. chapter 6, decoding pipeline synchronization , discusses the mechanism for synchronizing the internal decoder modules to the incoming data stream. chapter 7, the fec decoder pipeline , describes the various logic modules that comprise the fec decoding pipeline. chapter 8, L64724 speci?cations , describes the electrical and mechanical characteristics of the L64724. appendix a, programming the L64724 using the serial bus protocol , provides information on how to program the L64724 using its serial bus protocol. appendix b, L64724 application notes , provides application information on connecting the L64724 in your circuit and programming it to meet your needs. appendix c, programming the serializer , discusses the programming of the serializer module. appendix d, a/d converters , discusses the analog-to-digital converters used in the L64724 device. appendix e, L64724 on-chip microcontroller , summarizes the features of the L64724 on-chip microcontroller. related publications european digital video broadcast standard, dtvb 1110 revision 7. this document is available from: dvb project of?ce european broadcasting union ancienne route, 17a grand saconnex geneva, switzerland lsi logic l64002 mpeg-2 audio/video decoder technical manual , document no. db14-000004-00. order no. i14011 lsi logic l64007 mpeg-2, dvb and tsat transport demultiplexer technical manual, document no. db14-000007-00. L64724tm_300.book page xii friday, april 14, 2000 2:17 pm
preface xiii conventions used in this manual the ?rst time a word or phrase is de?ned in this manual, it is italicized. the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre?x 0x before the numberfor example, 0x32cf. binary numbers are indicated by the pre?x 0b before the numberfor example, 0b0011. operations on registers are referred to using the binary numbers 0 and 1. output signal levels are referred to by the designations high and low. example: set the xctr0 register bit to 1 to force the xctr_out0 pin high. L64724tm_300.book page xiii friday, april 14, 2000 2:17 pm
xiv preface L64724tm_300.book page xiv friday, april 14, 2000 2:17 pm
L64724 satellite receiver 1-1 chapter 1 introduction this chapter introduces the L64724 satellite receiver from lsi logic. the L64724 is designed speci?cally to meet the needs of satellite broadcast digital tv and is compliant with the european digital video broadcast (dvb-s) standard and the technical speci?cations for dss systems. the sections in this chapter are: section 1.1, general description section 1.2, typical application section 1.3, features summary 1.1 general description the L64724 satellite receiver contains two main blocks: a bpsk/qpsk demodulator and a concatenated fec decoder. the bpsk/qpsk module performs binary and quadrature phase-shift keying (bpsk/qpsk) demodulation, a method of extracting a digital signal from a phase-modulated analog signal. the concatenated fec decoder is a complete concatenated forward error correction decoder that uses a viterbi inner code and a reed- solomon outer code. the fec decoding pipeline also contains all of the necessary synchronization, deinterleaving, and scrambling functions for a complete decoding solution. lsi logic fabricates the L64724 using a 3.3-volt hcmos process technology. the L64724 provides maximum integration and ?exibility for system designers at a minimum cost. it contains an on-chip dual 6-bit analog-to- digital converter (adc) as well as an on-chip microcontroller. the microcontroller controls the tuner as well as acquisition and tracking, L64724tm_300.book page 1 friday, april 14, 2000 2:17 pm
1-2 introduction which eliminates interaction from the main cpu, freeing up the cpu to perform other functions. the number of external components required to build a system is minimal because both clock and carrier loops are incorporated into the device. figure 1.1 is a block diagram of the L64724. figure 1.1 L64724 block diagram microcontroller data and address bus filter matched filter carrier loop control agc control internal microcontroller interface i q timing loop control output control demi demq 1/t descrambler reed- solomon decoder convolutional deinterleaver reed- solomon syncronizer viterbi decoder viterbi synchronizer channel output (mpeg-2 transport stream) bpsk/qpsk demodulator fec decoder pipeline channel input from satellite microcontroller data and address bus dual adc interpolator/decimation n/t clk external microcontroller interface L64724tm_300.book page 2 friday, april 14, 2000 2:17 pm
typical application 1-3 1.2 typical application a typical application of the L64724 is satellite digital tv reception in accordance with the dvb 1110 rev. 7 standard. figure 1.2 shows the L64724 satellite receiver implemented in a typical satellite receiver set- top decoder box. also shown are two other lsi logic products: l64008 mpeg-2 cpu transport demultiplexer l64005 mpeg-2 audio/video decoder L64724tm_300.book page 3 friday, april 14, 2000 2:17 pm
1-4 introduction figure 1.2 set-top decoder box block diagram co [7:0] pcm tuner L64724 transport 256k x 16 vcxo dram sdram pal / ntsc ntsc pa l s-video l-speaker r-speaker 27 mhz audio/video pes ccir601video pcm audio encoder audio dac satellite in 16 16 16 dram optional high-speed port 8 audio oversampling clock / / 8 / 8 / 3 / / 8 / 2 / microcontroller data and address bus audio/video (required) 1m x 16 serial bus control demux decoder l64008 l64005 / L64724tm_300.book page 4 friday, april 14, 2000 2:17 pm
features summary 1-5 1.3 features summary this section summarizes the main features of the L64724. subsequent chapters describe these features in more detail. on-chip self-tuning microcontroller acquisition and tracking, eliminating microprocessor interaction, and simplifying software development. supports dvb and dss system speci?cations. bpsk/qpsk demodulation rates from 1 to 45 mbaud. matched ?lter (square root raised cosine ?lter with roll-off factor of 20% or 35%). antialiasing ?lters for operation from 1 to 45 mbaud without switching external saw ?lters or the need for low-pass ?lters. on-chip digital clock synchronization. on-chip digital carrier synchronization, featuring a frequency sweep capability for signal acquisition. auto-acquisition demodulator mode and tuner control through an on-chip microcontroller. integrated phase-locked loop (pll) for clock synthesis, allowing the use of a fundamental mode crystal. dual adc. fast channel switching mode. power estimation for agc control. programmable viterbi decoder module for the following rates: 1/2, 2/3, 3/4, 5/6, 6/7, and 7/8. (204/188), (146/130) reed-solomon decoder. auto-synchronization for the viterbi decoder. programmable synchronization for the deinterleaver, reed-solomon decoder, and descrambler. bit error monitoring for channel performance measurements. deinterleaver (dvb and dss). L64724tm_300.book page 5 friday, april 14, 2000 2:17 pm
1-6 introduction serial host interface compatible with the lsi logic serial control bus interface. power-down mode. L64724tm_300.book page 6 friday, april 14, 2000 2:17 pm
L64724 satellite receiver 2-1 chapter 2 L64724 signal de?nitions this chapter describes the L64724 signals and is divided into the following sections: section 2.1, channel interface section 2.2, channel clock interface section 2.3, phase-locked loop (pll) interface section 2.4, control signals interface section 2.5, agc/clock control interface section 2.6, channel data output interface section 2.7, analog-to-digital converter (adc) interface section 2.8, microcontroller interface figure 2.1 shows the logic symbol for the L64724. L64724tm_300.book page 1 friday, april 14, 2000 2:17 pm
2-2 L64724 signal de?nitions figure 2.1 L64724 logic symbol as shown in figure 2.1 , the L64724 has the following major interfaces: channel channel clock pll channel interface pll interface microcontroller interface control signals interface channel data output interface adc interface channel clock interface ibypass[5:0] qbypass[5:0] clk xoin xoout lp2 pclk pllagnd pllvdd pllvss iddtn reset xctr_in xctr_out[3:0] lclk 8 4 3 2 8 bclkout co[7:0] coen dvalidout erroroutn fstartout ibias adcvssi/q adcvddi/q adcvrefi/q adcvrefni/q pwrp a[2:0] asn csn d[7:0] dtackn/wait dtack/pol host_mode intn read/write ivin qvin agc/clock control interface 2 2 2 6 6 qbias L64724tm_300.book page 2 friday, april 14, 2000 2:17 pm
channel interface 2-3 control signals agc/clock control channel data output adc microcontroller the following signal descriptions are listed according to the major interface groups. 2.1 channel interface the channel interface is the input path to the L64724 satellite receiver. the two signals ivin and qvin are the i and q streams from the satellite tuner circuit. the clk signal strobes in the data signals. ibypass[5:0] channel data input the ibypass[5:0] signals form the digital received i channel data input bus, which supplies the i stream to the L64724 when the adc is bypassed. ivin i channel data input the ivin signal is the analog received i channel data input bus, which supplies the i stream to the L64724. qbypass[5:0] q channel data input the qbypass[5:0] signals form the digital received q channel data input bus, which supplies the q stream to the L64724 when the adc is bypassed. qvin q channel data input the qvin signal is the analog received q channel data input bus, which supplies the q stream to the L64724. L64724tm_300.book page 3 friday, april 14, 2000 2:17 pm
2-4 L64724 signal de?nitions 2.2 channel clock interface the channel clock interface consists of the clock and crystal oscillator signals. clk ivin/qvin input clock input clk is a positive, edge-triggered clock that strobes input data to the L64724. xoin crystal oscillator in input the xoin pin is used for a crystal oscillator or external reference clock input. xoout crystal oscillator out output the xoout pin is the crystal oscillator output pin. 2.3 phase-locked loop (pll) interface the pll circuitry multiplies the external clock signal by 2, 3, or 4 times the symbol rate, based on the viterbi code rate. lclk decimated clock output output the L64724 internal clock generation module generates the lclk signal. lclk is derived from clk by dividing by the value of the clk_div2 parameter (group 4, apr 22 and 23). lp2 input to vco input the lp2 signal is the input to the internal voltage- controlled oscillator. it is normally connected to the output of an external rc timing circuit. pclk pll clock output output the L64724 internal pll clock synthesis module generates the pclk signal. the clk signal drives the pll. the pll clock synthesis module can be con?gured to generate a pclk rate that is appropriate for all data rates. pllagnd pll analog ground input pllagnd is the analog ground pin for the pll module and is normally connected to the system ground plane. L64724tm_300.book page 4 friday, april 14, 2000 2:17 pm
control signals interface 2-5 pllvdd pll power input pllvdd is the power supply pin for the pll module and is normally connected to the system power (v dd ) plane. pllvss pll ground input pllvss is the ground pin for the pll module and is normally connected to the system ground plane. 2.4 control signals interface the control signals interface controls the operation of the L64724 and is not associated with any particular interface. iddtn test input the iddtn pin is an lsi logic internal test pin. set the iddtn pin low for normal operation. reset reset input reset is an active-high signal that, when asserted, resets all internal data paths. the reset signal resets all of the group 2 and group 3 registers and some of the group 5 register bits. group 4 registers are unaffected. reset timing is asynchronous to the device clocks. the reset signal performs the same operation as the reset bits speci?ed in the group 4 apr 55 register. pclk must be running for reset to take effect. xctr_in control input input the xctr_in pin is an external input control pin. it is sensed by reading the xctr_in bit (d6) in the group 3, apr 6 register. xctr_out[3] control output/sync status flag output the xctr_out[3] pin indicates the synchronization status for one of three synchronization modules in the L64724. the modules are the viterbi decoder, reed- solomon deinterleaver (di/rs), and descrambler. for any of the three synchronization outputs, the xctr_out[3] signal, when asserted, indicates that synchronization has been achieved for the sync module chosen using the sss[1:0] bits (group 4, apr16). when deasserted, the signal indicates an out-of-synchronization condition. L64724tm_300.book page 5 friday, april 14, 2000 2:17 pm
2-6 L64724 signal de?nitions xctr_out[2:0] control output output the xctr_out[2:0] pins are external output control pins. they are set by programming the corresponding bits in the group 4, apr 55 register. xctr_out[1] can function as the serial clock (sclk) signal, and xctr_out[0] can function as the serial data (sdata) signal. 2.5 agc/clock control interface pwrp power control output the pwrp signal is the positive modulated output used for power control and can drive an external passive rc ?lter that feeds the tuner gain control stage. 2.6 channel data output interface the channel data output interface is the output path from the L64724. it is typically connected to the input of the transport demultiplexer in a set-top decoder application. bclkout byte clock out output the bclkout output signal is a strobe that indicates valid data bytes on the co[7:0] bus when the L64724 is in parallel channel output mode. the bclkout signal cycles once every valid output data byte and is used by the transport demultiplexer to latch output data from the L64724 at the bclkout rate. the bclkout signal must be disregarded in serial channel output mode. co[7:0] channel data out output the co[7:0] signals form the decoded output data port. when the of bit is 1 (group 4, apr17), the L64724 operates in the parallel channel output mode. in this mode, the L64724 outputs the channel data as 8-bit wide parallel data on the co[7:0] signals. in serial channel output mode (of = 0) the L64724 outputs the channel data as serial data on co[0]. the data is latched on every bit clock cycle. the chronological ordering in serial channel output mode is msb oldest, lsb newest. L64724tm_300.book page 6 friday, april 14, 2000 2:17 pm
analog-to-digital converter (adc) interface 2-7 coen channel output enable input when asserted, the coen signal enables the erroroutn, co[7:0], dvalidout, bclkout, and fstartout pins. operation of the receiver continues regardless of the state of the coen signal. dvalidout valid data out output the dvalidout signal indicates that the co[7:0] signals contain the corrected channel data. new data is valid on the co[7:0] signals when the dvalidout signal is asserted. dvalidout is not asserted during the propa- gated check and gap bytes. the dvalidout signal is deasserted after the fec_rst register bit (group 4, apr 55) is set to a 1. erroroutn error detection flag output the L64724 asserts the erroroutn pin (low) to ?ag uncorrectable errors. the L64724 asserts the erroroutn signal at the beginning of any frame that contains an uncorrectable error, and deasserts it at the end of the frame if the error condition is removed. the erroroutn signal is exactly aligned with the output data stream and is asserted after the fec_rst register bit (group 4, apr 55) is set to a 1. the errorout_invert bit (group 4, apr 31), when set to 1, changes the active state of the erroroutn signal from active-low to active-high. fstartout frame start output output the L64724 asserts the fstartout signal during the ?rst bit of every frame with valid data in serial channel output mode and during the ?rst byte in parallel channel output mode. fstartout is valid only when the dvalidout signal is asserted. the fstartout signal is deasserted after the fec_rst register bit (group 4, apr 55) is set to a 1. 2.7 analog-to-digital converter (adc) interface the adc module converts the incoming ivin and qvin signals into an internal 6-bit digital representation for processing. the following pins support the adc module. L64724tm_300.book page 7 friday, april 14, 2000 2:17 pm
2-8 L64724 signal de?nitions adcvddi/q adc power input adcvddi/q are the analog power supply pins for the adc module and are normally connected to the system power (v dd ) plane. adcvrefi adc i reference input this pin supplies vdd to the internal reference generator. adcvrefni adc negative i reference input this pin supplies vrefn to the internal adc cells. adcvrefq adc q reference input this pin is not used and should be left unconnected. any other connection will cause unpredictable and unreliable operation of the device. adcrefnq adc negative q reference input this pin supplies the ground to the internal adc cell. adcvssi/q adc analog ground input adcvssi/q are the analog ground pins for the adc module and are normally connected to the system ground plane. ibias current bias i input the ibias pin supplies the current bias for the adcs. qbias current bias q input this pin is used by lsi logic for internal purposes, and should be connected as shown in figure d.2. any other connection will cause unpredictable and unreliable operation of the device. 2.8 microcontroller interface the microcontroller interface connects the L64724 to a microcontroller such as the 64008. a[2:0] address input the a[2:0] signals form the receiver address bus. the address bus is used in conjunction with an 8-bit data bus d[7:0], a read/write strobe (read/write), a chip select strobe (cs), and an address strobe (as) to select, read, and write internal registers. L64724tm_300.book page 8 friday, april 14, 2000 2:17 pm
microcontroller interface 2-9 asn address strobe input the asn signal is an active-low address strobe input. the L64724 latches the address on the a[2:0] signals on the falling edge of the asn signal. csn chip select input the csn signal is an active-low chip select strobe input. during a read cycle, the microcontroller must assert csn (low) to access the on-chip data registers. the microcontroller must latch the data from the L64724 on the rising edge of csn. during a write cycle, csn must be asserted prior to data being valid from the microcon- troller to the L64724. after the data has met the minimum setup time, the microcontroller deasserts csn (high) to strobe the data. there is a minimum write time to allow for internal synchronization. setup and hold times are measured with respect to the falling edge of csn. d[7:0] data bidirectional the d[7:0] signals form the bidirectional data bus, which is an input data bus when data is written to the L64724 chip and a data output bus when the L64724 chip is read in parallel host interface mode 1 (host_mode pin high). the data lines are 3-stated when not being read or written. when serial host interface mode is selected (host_mode pin low), d[0] is used as the serial clock (sclk) signal to synchronize the transfer of serial data on the serial data (sdata) pin. in serial host interface mode, xctr_out[1] functions as sdata, d[1] is used as the sdata signal to transfer serial data, and d[3:2] are used as the two lsbs of the L64724 slave address. dtack/pol data acknowledge/wait polarity input the dtack/pol signal determines the polarity of the data acknowledge/wait signal. when the dtack/pol signal is low, dtackn/wait is active-low. when the dtack/pol signal is high, the dtackn/wait signal is active-high. 1. serial mode is the recommended interface mode. lsi logic does not recommend parallel mode for new designs. L64724tm_300.book page 9 friday, april 14, 2000 2:17 pm
2-10 L64724 signal de?nitions dtackn/wait data acknowledge/wait output the dtackn/wait signal is an output indicating that the transaction on the d[7:0] bus has been completed. it is active-low when dtack/pol is low and active-high when dtack/pol is high. do not base the chip pro- gramming on this signal. host_mode serial or parallel host interface select input when the host_mode signal is deasserted, it selects the serial host interface mode. when it is asserted, it selects the parallel host interface mode 1 . intn interrupt output the L64724 asserts the intn signal (low) when an internal unmasked interrupt ?ag is set. the intn signal remains asserted as long as the interrupt condition persists and the interrupt ?ag is not masked. read/write read/write strobe input the microcontroller asserts the read/write signal (high) to indicate that the current transaction is a read from the L64724, and deasserts it (low) to indicate that it is a write to the L64724. 1. serial mode is the recommended interface mode. lsi logic does not recommend parallel mode for new designs. L64724tm_300.book page 10 friday, april 14, 2000 2:17 pm
L64724 satellite receiver 3-1 chapter 3 L64724 registers this chapter discusses the L64724 internal registers. it also provides a description of the internal memory mapping and describes how to access the registers from the system interface. this chapter is intended primarily for system programmers who are developing software drivers and contains the following sections: section 3.1, L64724 register overview section 3.2, reset and how it affects registers section 3.3, groups 0 and 1: address pointer register section 3.4, group 2: system mode and system status registers section 3.5, group 3: status registers section 3.6, group 4: con?guration registers section 3.7, group 5: self-tuning microcontroller registers section 3.8, group 6: reserved (internal use only) section 3.9, group 7: arbiter control register section 3.10, reset effect on register bits section 3.11, internal data path reset effects this chapter provides complete information on how to use these registers, but does not provide information on how to program the registers for a speci?c application. see appendix b, "L64724 application notes," for some programming examples. 3.1 L64724 register overview the L64724 registers and memory resources are divided into eight groups, group 0 through group 7. L64724tm_300.book page 1 friday, april 14, 2000 2:17 pm
3-2 L64724 registers groups 0 and 1 contain the address pointer register. this pointer is used to address the registers in groups 2, 3, and 4. group 2 addresses the system mode register when written and the system status register when read. group 3 contains the status registers. group 4 contains the con?guration registers. group 5 contains the program space for the on-board microprocessor. group 6 is reserved for internal use only. group 7 is used for arbiter control. table 3.1 shows the complete register map for the L64724 satellite receiver. figure 3.1 shows a simpli?ed diagram of the L64724 register groups. table 3.1 register overview group name function page 0 apr0 address pointer register, lsb 3-8 1 apr1 address pointer register, msb 3-8 2 smr/sts system mode/system status registers 3-9 3 status status registers 3-23 4 config con?guration registers 3-33 5 micro microcontrol registers 3-77 6 reserved reserved 3-81 7 arbiter arbiter control register 3-81 L64724tm_300.book page 2 friday, april 14, 2000 2:17 pm
L64724 register overview 3-3 figure 3.1 register file structure to reduce the number of memory locations occupied by the L64724 in microprocessor memory, the L64724 uses a pair of address pointer registers (apr0 and apr1). the address pointer registers have an auto-increment feature that simpli?es the initialization procedure and reduces the number of memory cycles needed to read or write the registers. the address pointer and auto-increment features are used whenever you access groups 2, 3, and 4. the L64724 automatically points to the next register entry after you complete an access to one of the three groups. when writing or reading register groups 3 and 4, it is easier to initially set apr0 and apr1 to zero and let the auto-increment mechanism step through all the locations within the group. for example, to access the pll_n con?guration register 0 (group 4, apr 0), ?rst set apr0 and apr1 to 0x00 by writing a zero to addresses 0 and 1, then set a[2:0] to 0b100. the value of 0b100 for address a[2:0] selects group 4. register apr0 apr1 smr/sts status config micro group 3: status registers group 4: con?guration registers reserved arbiter 0 1 2 ... 22 23 0 1 ... 61 69 0 1 2 3 4 5 6 7 group 5: microcontrol registers 0 1 ... 519 520 group 7: arbiter control register 0 group group 2: system mode/system status registers 0 1 2 3 0 1 2 3 smr sts L64724tm_300.book page 3 friday, april 14, 2000 2:17 pm
3-4 L64724 registers the L64724 has an internal 8-bit architecture. most registers are 8 bits wide, while some are either 16 or 24 bits wide. all registers are memory-mapped to the system with 8-bit resolution. when you are accessing a register that is wider than 8 bits, you must read or write two or three 8-bit sections. the sections are divided into the least-signi?cant byte (lsb), the middle-signi?cant byte (mb), and the most-signi?cant byte (msb). each 8-bit section is assigned a speci?c address, and requires an individual memory cycle during programming. 3.1.1 parallel host interface mode 1 the L64724 is addressable through either a serial or a parallel host interface. the interface used depends on the state of the host_mode input pin when the L64724 is reset. the interface is selected as follows: host_mode pin high = parallel host interface mode host_mode pin low = serial host interface mode the interface mode cannot be changed once the part is in operation. the following paragraphs show the steps required to read and write the L64724 registers when you are in parallel host interface mode. serial host interface mode is discussed in section 3.1.2, serial host interface mode, page 3-6 , and appendix a, "programming the L64724 using the serial bus protocol," . figure 3.2 through figure 3.5 demonstrate read and write operation through the parallel microprocessor interface. note: the pclk signal must operate for the user to be able to access groups 2 and 3. group 4, however, can be programmed in the absence of pclk. to read and write registers using the parallel interface mode, follow these steps: 1. issue a hard reset to the L64724 for three clock cycles, as shown in figure 3.2 . wait for the wake-up time (t wk ), which is 280 pclk cycles, before continuing. 1. serial mode is the recommended interface mode. lsi logic does not recommend parallel mode for new designs. L64724tm_300.book page 4 friday, april 14, 2000 2:17 pm
L64724 register overview 3-5 figure 3.2 issue a hard reset 2. set the apr0 and apr1 registers to zero by writing a zero to groups 0 and 1. see figure 3.3 . figure 3.3 initialize apr0 and apr1 to zero 3. write to the con?guration registers in group 4. because the aprs were both initialized to zero, the ?rst location written in group 4 is location zero, the second location written is 1, and so on. as long as the address lines a[2:0] contain the value 4, the auto-increment mechanism advances to the next location in group 4 with every low-to-high transition of csn. figure 3.4 and figure 3.5 show the ?rst two writes to group 4. the 0x82 and 0x04 values shown for d[7:0] are typical values for locations 0 and 1, respectively. see section 3.6, group 4: con?guration registers, page 3-33 , for more details on the data values. pclk reset 3 pclk cycles 01 00 00 csn d[7:0] asn a[2:0] read/write dtackn L64724tm_300.book page 5 friday, april 14, 2000 2:17 pm
3-6 L64724 registers figure 3.4 write locations 0 and 1 in group 4 4. you can also choose to read back the group 4 configuration registers, as demonstrated in figure 3.5 . just set apr0 and apr1 to zero (see figure 3.3 ) and step through the configuration locations using a value of 4 for a[2:0]. the read/write signal is asserted, and the auto- increment mechanism selects location 0, then location 1, and so on. figure 3.5 read back group 4 3.1.2 serial host interface mode setting the host_mode pin low during reset places the L64724 in serial host interface mode. when the L64724 is addressed using the serial interface, it must ?rst be programmed with a 2-bit slave address before any other read or write cycles. appendix a, "programming the L64724 using the serial bus protocol," contains a detailed description of the protocol used when programming the L64724 in serial host interface mode. csn d[7:0] asn a[2:0] read/write dtackn 44 04 82 csn d[7:0] asn a[2:0] read/write dtackn 44 04 82 L64724tm_300.book page 6 friday, april 14, 2000 2:17 pm
reset and how it affects registers 3-7 3.2 reset and how it affects registers there are three separate resets available on the L64724, as follows: the hardware reset pin the demod_rst register bit (group 4, apr 55, bit 1) the fec_rst register bit (group 4, apr 55, bit 0). each reset affects the registers differently, as follows: toggling the hardware reset pin resets all of the group 2 and group 3 registers and some of the group 4 registers. registers in group 4 are unaffected. setting the demod_rst bit in the external output control bits and reset register (group 4, apr 55, bit 1) affects only the bits in group 3 registers that are directly concerned with the demodulator circuitry. setting the fec_rst bit in the external output control bits and reset register (group 4, apr 55, bit 0) resets the system mode/status registers (group 2) and any bits in group 3 registers that are directly concerned with the fec circuitry. registers in group 4 are unaffected by any of the reset operations. the contents of the group 4 registers are random immediately after power-up, and retain their last known value after any of the three reset operations listed above. the following steps should be followed when resetting the L64724: 1. issue an active-high reset pulse to the reset pin. the reset pulse width must be in accordance with the parameter t rwh (see figure 8.4 ). 2. program the con?guration (group 4) registers to their proper values. 3. issue a soft reset by setting the demod_rst bit and the fec_rst bits t o a 1 (group 4, apr 55). the bits are self-resetting, and do not have to be cleared. 4. after the reset pin has been deasserted (low), wait the wake-up time amount speci?ed by the parameter t wk (see figure 8.4 ). L64724tm_300.book page 7 friday, april 14, 2000 2:17 pm
3-8 L64724 registers 5. the L64724 is now in the acquisition mode. when data is applied at the L64724 input, it is ready to start demodulating and decoding. for details on how reset affects the various register bits, see section 3.10, reset effect on register bits, page 3-82 . 3.3 groups 0 and 1: address pointer register the address pointer register (apr) is a 13-bit r/w register that points to the registers in groups 2, 3, and 4. it is accessed when a[2:0] = 0b000 and 0b001. before accessing a register location from group 2, 3, or 4, you must initialize the apr contents with the address of the ?rst register entry that you are going to read or write. the apr automatically increments after reading or writing a byte within a group 2 (a[2:0] = 0b010), group 3 (a[2:0] = 0b011) group 4 (a[2:0] = 0b100) or group 5 (a[2:0] = 0b101) register. two consecutive writes are required to load the complete apr. the ?rst write is to group 0 to load the eight lsbs, the second to group 1 to load the ?ve msbs. the apr can be read as well as written. group 1, data bus d[7:0] group 0, data bus d[7:0] the reserved bits in these registers are for lsi internal test procedures and future expansion and should always be set to zero. 12 0 address pointer, apr[12:0] 754 07 0 reserved apr[12:8] apr[7:0] L64724tm_300.book page 8 friday, april 14, 2000 2:17 pm
group 2: system mode and system status registers 3-9 to access a group 2, 3, or 4 register: 1. initialize the apr with the address of the ?rst register you want to access within a particular register group. you should write both bytes of the apr. 2. read or write the ?rst register within the register group you are accessing using the appropriate register group address. the addresses are: group 20b010 group 30b011 group 40b100 group 50b101 3. if the register is a 16-bit register, just perform another read or write to the group register address to access the second byte. the apr increments automatically. when you are through, the apr automatically points to the next register in the group. 3.4 group 2: system mode and system status registers group 2 contains two 32-bit registers, the system mode register (smr) and the system status register (sts). the system mode register is accessed by writing the group 2 address, and the system status register is accessed by reading the group 2 address. because the L64724 has an 8-bit architecture, each 32-bit register is accessed as four 8-bit registers. the microprocessor accesses these registers by setting a[2:0] = 0b010. it can access these registers at any point during satellite receiver operation without interrupting the internal processing unit. note: the phase-locked loop must be locked (pclk running) for the status signals to be valid. L64724tm_300.book page 9 friday, april 14, 2000 2:17 pm
3-10 L64724 registers 3.4.1 system mode register (smr) the 32-bit system mode register (smr) is a write-only register that allows the external microprocessor to control the L64724. table 3.2 shows the smr map. the bits in the register are allocated as follows: smr[7:0] enable fec module interrupts. smr[23:8] enable the demodulator interrupts. smr[31:24] enable interrupts for the on-chip microcontroller. because the smr is arranged as four 8-bit registers, the microprocessor must perform four consecutive writes to the register address. the lower eight bits of the apr must be set to 0x00 in order to access bits smr[7:0]. the eight lsbs of the smr are accessed ?rst. the auto- increment mechanism toggles the address pointer register after the ?rst access so that the next write goes to the smr[15:8] bits. if you want to access the smr starting with bytes 1, 2, or 3, set the apr equal to 0b01, 0b10, or 0b11, respectively. table 3.2 group 2 system mode register map (write-only) apr d7 d6 d5 d4 d3 d2 d1 d0 0 smr[7:0] vber_ie s3_ls_ie s3_s_ie s2_ls_ie s2_s_ie s1_ls_ie s1_s_ie reserved 1 smr[15:8] clk_lk_ ie clk_llk_ ie cp_lk_ie cp_llk_ ie reserved = 0 cl_fs_ll_ ie cl_fs_ul_ ie 2 smr[23:16] reserved tl_fs_ll_ ie tl_fs_ul_ ie 3 smr[31:24] uc_ie7 uc_ie6 uc_ie5 uc_ie4 uc_ie3 uc_ie2 uc_ie1 uc_ie0 L64724tm_300.book page 10 friday, april 14, 2000 2:17 pm
group 2: system mode and system status registers 3-11 the following register diagram shows the bit organization of smr[7:0]. descriptions of the bits follow the register diagram. the L64724 clears all bits in the smr to zero after a software or hardware reset. vber_ie viterbi bit error rate monitor interrupt enable 7 the microprocessor sets the vber_ie bit to enable an interrupt when the viterbi decoder reaches the period specified by vmdc2 (the period over which the viterbi bit errors are counted). the L64724 always sets the vber bit in the sts register when this condition occurs. s3_ls_ie stage 3 loss of synchronization interrupt enable 6 the microprocessor sets the s3_ls_ie bit to enable an interrupt when descrambler synchronization is lost. s3_ls_ie is not used in dss mode. s3_s_ie stage 3 synchronization interrupt enable 5 the microprocessor sets the s3_s_ie bit to enable an interrupt when descrambler synchronization is established. s3_s_ie is not used in dss mode. apr d7 d6 d5 d4 d3 d2 d1 d0 0 smr[7:0] vber_ie s3_ls_ie s3_s_ie s2_ls_ie s2_s_ie s1_ls_ie s1_s_ie reserved vber_ie de?nition 0 disable interrupt for viterbi ber count 1 enable interrupt for viterbi ber count s3_ls_ie de?nition 0 disable interrupt for stage 3 loss of synchronization 1 enable interrupt for stage 3 loss of synchronization s3_s_ie de?nition 0 disable interrupt for stage 3 synchronization 1 enable interrupt for stage 3 synchronization L64724tm_300.book page 11 friday, april 14, 2000 2:17 pm
3-12 L64724 registers s2_ls_ie stage 2 loss of synchronization interrupt enable 4 the microprocessor sets the s2_ls_ie bit to enable an interrupt when deinterleaver/reed-solomon decoder synchronization is lost. s2_s_ie stage 2 synchronization interrupt enable 3 the microprocessor sets the s2_s_ie bit to enable an interrupt when deinterleaver/reed-solomon decoder synchronization is established. s1_ls_ie stage 1 loss of synchronization interrupt enable 2 the microprocessor sets the s1_ls_ie bit to enable an interrupt when viterbi decoder synchronization is lost. s1_s_ie stage 1 synchronization interrupt enable 1 the microprocessor sets s1_s_ie to enable an interrupt when viterbi decoder synchronization is established. reserved reserved 0 the reserved bit is for lsi logic internal use only and should always be cleared to 0. the following register diagram shows the bit organization of smr[15:8]. descriptions of the bits follow the register diagram. the L64724 sets all the bits in smr[15:8] to 0 after a software or a hardware reset. s2_ls_ie de?nition 0 disable interrupt for stage 2 loss of synchronization 1 enable interrupt for stage 2 loss of synchronization s2_s_ie de?nition 0 disable stage 2 synchronization interrupt 1 enable stage 2 synchronization interrupt s1_ls_ie de?nition 0 disable stage 1 loss of synchronization interrupt 1 enable stage 1 loss of synchronization interrupt s1_s_ie de?nition 0 disable stage 1 synchronization interrupt 1 enable stage 1 synchronization interrupt L64724tm_300.book page 12 friday, april 14, 2000 2:17 pm
group 2: system mode and system status registers 3-13 clk_lk_ie timing lock detect interrupt enable 15 the microcontroller sets the clk_lk_ie bit to enable an interrupt when timing lock is detected. the L64724 always sets the clk_lk bit in the sts register when this condition occurs. clk_llk_ie timing lock lost detect interrupt enable 14 the microcontroller sets the clk_llk_ie bit to enable an interrupt when timing lock loss is detected. the L64724 always sets the clk_llk bit in the sts register when this condition occurs. cp_lk_ie carrier phase lock detect interrupt enable 13 the microprocessor sets the cp_lk_ie bit to enable an interrupt when carrier phase lock is detected (car_lc = 1 in group 3, apr11). the L64724 always sets the cp_lk bit in the sts register when this condition occurs. cp_llk_ie carrier phase lock lost detect interrupt enable 12 the microprocessor sets the cp_llk_ie bit to enable an interrupt when carrier phase lock loss is detected apr d7 d6 d5 d4 d3 d2 d1 d0 1 smr[15:8] clk_lk_ie clk_llk_ie cp_lk_ie cp_llk_ie reserved = 0 cl_fs_ll_ie cl_fs_ul_ie clk_lk_ie de?nition 0 disable interrupt for timing lock detect 1 enable interrupt for timing lock detect clk_llk_ie de?nition 0 disable interrupt for timing lock lost detect 1 enable interrupt for timing lock lost detect cp_lk_ie de?nition 0 disable interrupt for carrier phase lock detect 1 enable interrupt for carrier phase lock detect L64724tm_300.book page 13 friday, april 14, 2000 2:17 pm
3-14 L64724 registers (car_lc = 0 in group 3, apr11). the L64724 always sets the cp_llk bit in the sts register when this condition occurs. reserved reserved [11:10] the reserved bits are for lsi logic internal use only and must always be cleared to 0. cl_fs_ll_ie frequency sweep lower limit reached interrupt enable 9 the microprocessor sets the cl_fs_ll_ie bit to enable an interrupt when the carrier loop frequency sweep has reached its lower limit. the L64724 always sets the cl_fs_ll bit in the sts register when this condition occurs. cl_fs_ul_ie frequency sweep upper limit reached interrupt enable 8 the microprocessor sets the cl_fs_ul_ie bit to enable an interrupt when the carrier loop frequency sweep has reached its upper limit. the L64724 always sets the cl_fs_ul bit in the sts register when this condition occurs. cp_llk_ie de?nition 0 disable interrupt for carrier phase lock loss detect 1 enable interrupt for carrier phase lock loss detect cl_fs_ll_ie de?nition 0 disable interrupt for frequency sweep lower limit reached detect 1 enable interrupt for frequency sweep lower limit reached detect cl_fs_ul_ie de?nition 0 disable interrupt for frequency sweep upper limit reached 1 enable interrupt for frequency sweep upper limit reached detect L64724tm_300.book page 14 friday, april 14, 2000 2:17 pm
group 2: system mode and system status registers 3-15 the following register diagram shows the bit organization of smr[23:16]. descriptions of the ?elds follow the register diagram. the L64724 sets all the bits in smr[23:16] to 0 after a software or a hardware reset. reserved reserved [23:18] the reserved bits are for lsi logic internal use only and must always be cleared to 0. tl_fs_ll_ie frequency sweep lower limit reached interrupt enable 17 the microprocessor sets the tl_fs_ll_ie bit to enable an interrupt when the timing loop frequency sweep has reached its lower limit. the L64724 always sets the tl_fs_ll bit in the sts register when this condition occurs. tl_fs_ul_ie frequency sweep upper limit reached interrupt enable 16 the microprocessor sets the tl_fs_ul_ie bit to enable an interrupt when the frequency sweep has reached its upper limit. the L64724 always sets the tl_fs_ul bit in the sts register when this condition occurs. apr d7 d6 d5 d4 d3 d2 d1 d0 2 smr[23:16] reserved tl_fs_ll_ie tl_fs_ul_ie tl_fs_ll_ie de?nition 0 disable interrupt for frequency sweep lower limit reached detect 1 enable interrupt for frequency sweep lower limit reached detect tl_fs_ul_ie de?nition 0 disable interrupt for frequency sweep upper limit reached 1 enable interrupt for frequency sweep upper limit reached detect L64724tm_300.book page 15 friday, april 14, 2000 2:17 pm
3-16 L64724 registers the following register diagram shows the bit organization of smr[31:24]. descriptions of the bits follow the register diagram. the L64724 clears all the bits in smr[31:24] to 0 after a software or a hardware reset. uc_ie7 uc interrupt 7 enable 31 the microprocessor sets the uc_ie7 bit to enable inter- rupt 7 from the on-chip microcontroller. the microcode can de?ne the meaning of interrupt 7; therefore this is a user-programmable interrupt. uc_ie6 uc interrupt 6 enable 30 the microprocessor sets the uc_ie6 bit to enable interrupt 6 from the on-chip microcontroller. the microcode can de?ne the meaning of interrupt 6; therefore, this is a user-programmable interrupt. uc_ie5 uc interrupt 5 enable 29 the microprocessor sets the uc_ie5 bit to enable interrupt 5 from the on-chip microcontroller. the microcode can de?ne the meaning of interrupt 5; therefore, this is a user-programmable interrupt. uc_ie4 uc interrupt 4 enable 28 the microprocessor sets the uc_ie4 bit to enable interrupt 4 from the on-chip microcontroller. the microcode can de?ne the meaning of interrupt 4; therefore, this is a user-programmable interrupt. uc_ie3 uc interrupt 3 enable 27 the microprocessor sets the uc_ie3 bit to enable interrupt 3 from the on-chip microcontroller. the microcode can de?ne the meaning of interrupt 3; therefore, this is a user-programmable interrupt. uc_ie2 uc interrupt 2 enable 26 the microprocessor sets the uc_ie2 bit to enable interrupt 2 from the on-chip microcontroller. the microcode can de?ne the meaning of interrupt 2; therefore, this is a user-programmable interrupt. apr d7 d6 d5 d4 d3 d2 d1 d0 3 smr[31:24] uc_ie7 uc_ie6 uc_ie5 uc_ie4 uc_ie3 uc_ie2 uc_ie1 uc_ie0 L64724tm_300.book page 16 friday, april 14, 2000 2:17 pm
group 2: system mode and system status registers 3-17 uc_ie1 uc interrupt 1 enable 25 the microprocessor sets the uc_ie1 bit to enable interrupt 1 from the on-chip microcontroller. the microcode can de?ne the meaning of interrupt 1; therefore, this is a user-programmable interrupt. uc_ie0 uc interrupt 0 enable 24 the microprocessor sets the uc_ie0 bit to enable interrupt 0 from the on-chip microcontroller. the microcode can de?ne the meaning of interrupt 0; therefore, this is a user-programmable interrupt. 3.4.2 system status register (sts) the sts register is a read-only register that provides the external microprocessor access to L64724 status information. table 3.3 shows the sts map. the sts register bits indicate the event that generated an internal interrupt condition. the interrupt status bits are set regardless of the enable interrupt bits in the smr register. the internal status is updated every L64724 clk. when the microprocessor reads the status, the current information is buffered in a special-purpose 32-bit sts buffer that locks the sts value until the end of the microprocessor read operation. table 3.3 group 2 system status register map (read-only) apr d7 d6 d5 d4 d3 d2 d1 d0 0 sts[7:0] vber s3_ls s3_s s2_ls s2_s s1_ls s1_s reserved 1 sts[15:8] clk_lk clk_llk cp_lk cp_llk set to 0 cl_fs_ll cl_fs_ul 2 sts[23:16] reserved tl_cl_fs_ ll tl_cl_fs_ ul 3 sts[31:24] uc_i7 uc_i6 uc_i5 uc_i4 uc_i3 uc_i2 uc_i1 uc_i0 L64724tm_300.book page 17 friday, april 14, 2000 2:17 pm
3-18 L64724 registers four consecutive read operations must be done to the same group 2 address (a[2:0] = 0b010) to access all four bytes of the status registers. the sts register bits are cleared to 0 after a hardware reset. they are also cleared each time a register byte is readwhen you read the eight lsbs, the eight lsb interrupts are cleared, and when you read the eight msbs, the eight msb interrupts are cleared. the following register diagram shows the bit organization of sts[7:0]. descriptions of the bits follow the register diagram. vber viterbi bit error rate flag 7 the L64724 sets the vber bit when the period speci?ed by vmdc2 (group 4apr 5, 6, and 7) is reached. the L64724 also generates an interrupt if the vber_ie bit in the smr is set. the L64724 clears the vber bit to 0 after a reset or a group 2 (sts) read. s3_ls stage 3 loss of synchronization flag 6 the L64724 sets the s3_ls bit when the descrambler synchronization module determines that synchronization is lost. it also generates an interrupt if the s3_ls_ie bit is set in the smr. the L64724 clears the s3_ls bit to 0 after a reset or a group 2 (sts) read. s3_s stage 3 synchronization flag 5 the L64724 sets the s3_s bit when the descrambler synchronization module acquires synchronization. the L64724 also generates an interrupt if the s3_s_ie bit is apr d7 d6 d5 d4 d3 d2 d1 d0 0 sts[7:0] vber s3_ls s3_s s2_ls s2_s s1_ls s1_s reserved vber de?nition 0 vmdc2 period not reached 1 vmdc2 period reached s3_ls de?nition 0 stage 3 synchronization status unchanged 1 loss of stage 3 synchronization detected L64724tm_300.book page 18 friday, april 14, 2000 2:17 pm
group 2: system mode and system status registers 3-19 set in the smr. the L64724 clears the s3_s bit to 0 after a reset or a group 2 (sts) read. s2_ls stage 2 loss of synchronization flag 4 the L64724 sets the s2_ls bit when the deinterleaver/reed-solomon decoder synchronization module determines that synchronization is lost. the L64724 also generates an interrupt if the s2_ls_ie bit is set in the smr. the L64724 clears the s2_ls bit to 0 after a reset or a group 2 (sts) read. s2_s stage 2 synchronization flag 3 the L64724 sets the s2_s bit when the deinterleaver/reed-solomon decoder synchronization module acquires synchronization. the L64724 also generates an interrupt if the s2_s_ie bit is set in the smr. the L64724 clears the s2_s bit to 0 after a reset or a group 2 (sts) read. s1_ls stage 1 loss of synchronization flag 2 the L64724 sets the s1_ls bit when the viterbi decoder synchronization module determines that synchronization is lost. the L64724 also generates an interrupt if the s1_ls_ie bit is set in the smr. the L64724 clears s1_ls to 0 after a reset or a group 2 (sts) read. s3_s de?nition 0 stage 3 synchronization status unchanged 1 stage 3 synchronization acquired s2_ls de?nition 0 stage 2 synchronization status unchanged 1 loss of stage 2 synchronization detected s2_s de?nition 0 stage 2 synchronization status unchanged 1 stage 2 synchronization acquired s1_ls de?nition 0 stage 1 synchronization status unchanged 1 loss of stage 1 synchronization detected L64724tm_300.book page 19 friday, april 14, 2000 2:17 pm
3-20 L64724 registers s1_s stage 1 synchronization flag 1 the L64724 sets the s1_s bit when the viterbi decoder synchronization module has acquired synchronization. the L64724 also generates an interrupt if the s1_s_ie bit is set in the smr. the L64724 clears s1_s to 0 after a reset or a group 2 (sts) read. reserved reserved 0 this bit is reserved for lsi logic internal use only. reading this bit will give unpredictable results. the following register diagram shows the bit organization of sts[15:8]. descriptions of the bits follow the register diagram. clk_lk timing lock established 15 the L64724 sets the clk_lk bit when timing lock is established. clk_llk timing lock lost 14 the L64724 sets the clk_llk bit when timing lock is lost. s1_s de?nition 0 stage 1 synchronization status unchanged 1 stage 1 synchronization acquired apr d7 d6 d5 d4 d3 d2 d1 d0 1 sts[15:8] clk_lk clk_llk cp_lk cp_llk reserved = 0 cl_fs_ll cl_fs_ul clk_lk de?nition 0 timing lock status unchanged 1 timing lock established clk_llk de?nition 0 timing lock status unchanged 1 timing lock lost L64724tm_300.book page 20 friday, april 14, 2000 2:17 pm
group 2: system mode and system status registers 3-21 cp_lk carrier phase lock established 13 the L64724 sets the cp_lk bit when carrier phase lock is established. cp_llk carrier phase lock lost 12 the L64724 sets the cp_llk bit when carrier phase lock is lost. reserved reserved [11:10] the reserved bits are for lsi logic internal use only and must always be cleared to 0. cl_fs_ll frequency sweep lower limit reached 9 the L64724 sets the cl_fs_ll bit when the lower limit of the carrier loop frequency sweep is reached. cl_fs_ul frequency sweep upper limit reached 8 the L64724 sets the cl_fs_ul bit when the upper limit of the carrier loop frequency sweep is reached. the following register diagram shows the bit organization of sts[23:16]. descriptions of the ?elds follow the register diagram. cp_lk de?nition 0 carrier phase lock status unchanged 1 carrier phase lock established cp_llk de?nition 0 carrier phase lock status unchanged 1 carrier phase lock lost fs_ll de?nition 0 frequency sweep status unchanged 1 frequency sweep lower limit reached fs_ul de?nition 0 frequency sweep status unchanged 1 frequency sweep upper limit reached L64724tm_300.book page 21 friday, april 14, 2000 2:17 pm
3-22 L64724 registers reserved reserved [23:18] these bits are reserved for lsi logic internal use only. the bits, when read, return a value of zero. tl_cl_fs_ll frequency sweep lower limit reached 17 the L64724 sets the tl_cl_fs_ll bit when the lower limit of the timing loop frequency sweep is reached. tl_cl_fs_ul frequency sweep upper limit reached 16 the L64724 sets the tl_cl_fs_ul bit when the upper limit of the timing loop frequency sweep is reached. the following register diagram shows the bit organization of sts[31:24]. the microcontroller interrupt register (uc_i) bits are reset after a hardware reset. they are also reset each time the register byte is read. the definition of each interrupt bit can be determined by the microcode. the interrupts are user-defined. apr d7 d6 d5 d4 d3 d2 d1 d0 2 sts[23:16] reserved tl_cl_fs_ll tl_cl_fs_ul tl_cl_fs_ll de?nition 0 frequency sweep status unchanged 1 frequency sweep lower limit reached tl_cl_fs_ul de?nition 0 frequency sweep status unchanged 1 frequency sweep upper limit reached apr d7 d6 d5 d4 d3 d2 d1 d0 3 sts[31:24] uc_i7 uc_i6 uc_i5 uc_i4 uc_i3 uc_i2 uc_i1 uc_i0 L64724tm_300.book page 22 friday, april 14, 2000 2:17 pm
group 3: status registers 3-23 3.5 group 3: status registers group 3 consists of a number of internal status registers that are used for diagnostics and performance evaluation purposes. the registers are internally updated every pclk cycle and are read asynchronously. when the microprocessor reads the register, the current information is buffered in a special-purpose buffer that stores the value of the respective register until the end of the read operation. in particular, registers that occupy more than one byte are frozen when the ?rst byte is read. with the exception of the uc_status_bytes, the L64724 clears all the bits in the group 3 registers to 0 after a software or a hardware reset. the uc_status_bytes are cleared through hardware reset or the reset_mode bit, located in group 5, apr 520, bit 1. for a de?nition of software reset, see group 4, apr 55, fec_rst and demod_rst. table 3.4 shows the addresses and ?elds of the group 3 registers. table 3.4 group 3 register map apr d7 d6 d5 d4 d3 d2 d1 d0 0 reed-solomon corrected error count low byte, cec[7:0] 1 reed-solomon corrected error count high byte, cec[15:8] 2 reed-solomon uncorrected error count low byte, uec[7:0] 3 reed-solomon uncorrected error count high byte, uec[15:8] 4 viterbi bit error rate count low byte, vberc[7:0] 5 viterbi bit error rate count high byte, vberc[15:8] 6 demod_snr xctr_in reserved chip_id 7 nco frequency deviation, car_ncof[7:0] 8 nco frequency deviation, car_ncof[15:8] 9 nco frequency deviation, car_ncof[23:16] 10 agc loop voltage meter, pwr_lvl[7:0] 11 reserved uc_ active reserved car_lc reserved s3 s2 s1 12 reserved ri read back, ri[5:0] 13 reserved rq read back, rq[5:0] (sheet 1 of 2) L64724tm_300.book page 23 friday, april 14, 2000 2:17 pm
3-24 L64724 registers 3.5.1 reed-solomon corrected error count (group 3: apr 0 and 1) when read, the reed-solomon corrected error count (cec) register presents the corrected byte or bit error count since it was last reset. the bit or byte error count is a function of the rs_bit/byte_select con?guration bit (group 4, apr 31, d7). when the bit error count mode is chosen, the value in the register represents the bit error count, which is the cec multiplied by eight. when written, the register is reset to 0. the cec ?eld is 16 bits long. the lsb is located at apr 0, bit 0, and the msb at apr 1, bit 7. the cec count saturates (stops) when it reaches its maximum count (65,535), and the counter is not reset after it is read. when the register is written, the cec bits are cleared to 0. read/write: r/w reset value: 0x0000 14 reserved imq_ active viterbi code rate[2:0] 15 reserved 16 reserved 17 uc_status_byte0 [7:0] 18 uc_status_byte1 [7:0] 19 uc_status_byte2 [7:0] 20 uc_status_byte3 [7:0] 21 uc_status_byte4 [7:0] 22 demodulator snr estimate, snr[7:0] 23 reserved demodulator snr estimate, snr[11:8] table 3.4 group 3 register map (cont.) apr d7 d6 d5 d4 d3 d2 d1 d0 (sheet 2 of 2) apr d7 d0 0 reed-solomon corrected error count low byte, cec[7:0] apr d15 d8 1 reed-solomon corrected error count high byte, cec[15:8] L64724tm_300.book page 24 friday, april 14, 2000 2:17 pm
group 3: status registers 3-25 3.5.2 reed-solomon uncorrected error count (group 3: apr 2 and 3) when read, the reed-solomon uncorrected error count (uec) register presents the uncorrected blocks count since it was last reset. when written, the register is cleared to 0. the uec ?eld is 16 bits long. the lsb is located at apr 2, bit 0, and the msb at apr 3, bit 7. the uec count saturates (stops) when it reaches its maximum count (65,535), and the counter is not reset after it is read. when the register is written, the uec bits are cleared. read/write: r/w reset value: 0x0000 3.5.3 viterbi bit error rate count (group 3: apr 4 and 5) when read, the viterbi bit error rate count register presents the viterbi decoder bit error count during the time period speci?ed by vmdc2 (group 4, apr 5,6,7). the viterbi bit error rate count (vberc) ?eld is 16 bits long. the lsb is located at apr 4, bit 0, and the msb at apr 5, bit 7. the actual number of errors is equal to four times vberc. vberc is updated each time a viterbi error is encountered, and is reset at the beginning of each vmdc2 period. read/write: r reset value: 0x0000 3.5.4 control input, snr, and chip_id register (group 3: apr 6) the control input, snr, and chip_id register contains the demodulator signal-to-noise ratio (demod_snr) bit, the control input bit (xctr_in), and the chip_id bit. apr d7 d0 2 reed-solomon uncorrected error count low byte, uec[7:0] apr d15 d8 3 reed-solomon uncorrected error count high byte, uec[15:8] apr d7 d0 4 viterbi bit error rate count low byte, vberc[7:0] apr d15 d8 5 viterbi bit error rate count high byte, vberc[15:8] L64724tm_300.book page 25 friday, april 14, 2000 2:17 pm
3-26 L64724 registers read/write: r reset value: 0x0000 demod_snr demodulator signal to noise ratio 7 when read, the demod_snr bit gives an indication of the snr. when the snr is bad (above the threshold), the bit is 0. when the snr is good (below the threshold), the bit is 1. the thresholds are discussed in section 5.7.2.1, phase error estimator, page 5-16 , and shown in figure 5.7 . xctr_in external control input bit 6 when read, the xctr_in bit shows the logic level applied to the external control input (xctr_in) pin. reserved reserved [5:1] these bits are reserved. chip_id chip identi?cation 0 when read, this bit shows the stepping of the L64724 ic. when the chip_id bit is 1, it indicates that the L64724 ic is an L64724b. when the bit is 0, it indicates that the ic is an L64724a. 3.5.5 nco frequency deviation (group 3: apr 7, 8, and 9) the L64724 puts the result of the carrier loop nco (number-controlled oscillator) frequency measurement into the nco frequency deviation 24-bit register. the value, in hz, corresponds to the frequency deviation observed in the carrier loop as a function of the low noise block converter (lnb) drift. to see the updated 24-bit car_ncof value, ?rst access apr7. apr d7 d6 d5 d1 d0 6 demod _snr xctr_in reserved chip_id L64724tm_300.book page 26 friday, april 14, 2000 2:17 pm
group 3: status registers 3-27 reapbd/wpbrite: r reset value: 0x0000 3.5.6 automatic gain control (agc) loop voltage meter (group 3: apr 10) the L64724 stores the agc loop control voltage in the agc loop voltage meter register. see section 5.8.3, power level, page 5-22 ,for an equation that relates v agc and pwr_lvl[7:0]. see section b.1, L64724 qpsk demodulator acquisition and debugging tips, for more details on pwr_lvl[7:0]. read/write: r reset value: 0x00 3.5.7 carrier and fec synchronization status (group 3: apr 11) the carrier and fec synchronization status register contains the carrier loop and fec pipeline synchronization status bits. read/write: r reset value: 0x00 reserved reserved 7 this bit is reserved for lsi logic internal use only. when read, it returns an indeterminate value. apr d7 d0 7 car_ncof[7:0] apr d15 d8 8 car_ncof[15:8] apr d23 d16 9 car_ncof[23:16] apr d7 d0 10 pwr_lvl[7:0] apr d7 d6 d5 d4 d3 d2 d1 d0 11 reserved uc_active reserved = 0 car_lc reserved s3 s2 s1 L64724tm_300.book page 27 friday, april 14, 2000 2:17 pm
3-28 L64724 registers uc_active microcontroller active flag 6 the L64724 sets the uc_active bit to 1 to indicate that the internal microcontroller is running. reserved reserved 5 the reserved bit is for lsi logic internal use only and must always be set to 0. car_lc carrier phase lock flag 4 the L64724 sets the car_lc bit to 1 to indicate that the carrier phase lock detector is locked. reserved reserved 3 this bit is reserved for lsi logic internal use only. when read, it returns an indeterminate value. s3 stage 3 synchronization flag 2 the L64724 sets the s3 bit to 1 when the descrambler synchronization module is in synchronization. when this bit is 0, the descrambler module is not synchronized. the s3 bit is not valid in dss mode. s2 stage 2 synchronization flag 1 the L64724 sets the s2 bit to 1 when the deinterleaver/reed-solomon decoder synchronization module is in synchronization. when the bit is 0, the uc_active de?nition 0 internal microcontroller not active 1 internal microcontroller running car_lc de?nition 0 carrier phase lock detector out of lock 1 carrier phase lock detector locked s3 de?nition 0 descrambler out of sync 1 descrambler in sync L64724tm_300.book page 28 friday, april 14, 2000 2:17 pm
group 3: status registers 3-29 deinterleaver/reed-solomon decoder is not synchronized. s1 stage 1 synchronization flag 0 the L64724 sets the s1 bit to 1 when the viterbi decoder synchronization module is in synchronization. when the bit is 0, the viterbi decoder is not synchronized. 3.5.8 ri read back (group 3: apr 12) the ri readback register displays the digital value on the i channel input. read/write: r reset value: 0x00 reserved reserved [7:6] these bits are reserved for lsi logic internal use only. when read, they return an indeterminate value. ri ri read back [5:0] this register displays the value on the ri[5:0] input bus. note that pclk needs to be running for this feature to operate properly. 3.5.9 rq read back (group 3: apr 13) the rq readback register displays the digital value on the q channel input. s2 de?nition 0 deinterleaver/reed-solomon decoder out of synchronization 1 deinterleaver/reed-solomon decoder in synchronization s1 de?nition 0 viterbi decoder out of synchronization 1 viterbi decoder in synchronization apr d7 d6 d5 d0 12 reserved ri[5:0] L64724tm_300.book page 29 friday, april 14, 2000 2:17 pm
3-30 L64724 registers read/write: r reset value: 0x00 reserved reserved [7:6] these bits are reserved for lsi logic internal use only. when read, they return an indeterminate value. rq rq read back [5:0] this register displays the value on the rq[5:0] input bus. note that pclk needs to be running for this feature to operate properly. 3.5.10 viterbi code rate (group 3: apr 14) read/write: r reset value: 0x00 reserved reserved bits [7:4] these bits are reserved for lsi logic internal use only. when read, they return an indeterminate value. imq_active imq mode active 3 when the imq_active bit is 1, it indicates that the state machine has detected an imq inversion 1 and is compensating for it automatically. vcr viterbi code rate [2:0] these bits display the viterbi decoder code rate that was found during the acquisition process for the convolutional decoder. the viterbi code rate information in this register is meaningful only after synchronization has apr d7 d6 d5 d0 13 reserved rq[5:0] apr d7 d4 d3 d2 d0 14 reserved imq_ active viterbi code rate, vcr[2:0] 1. the q portion of the iq spectrum is inverted and the i portion is not inverted. L64724tm_300.book page 30 friday, april 14, 2000 2:17 pm
group 3: status registers 3-31 been achieved as indicated when the s1 bit in apr 11 is set to 1. 3.5.11 reserved (group 3: apr 15) read/write: r reset value: 0x00 reserved reserved bits [7:0] these bits are reserved for lsi logic internal use only. when read, they will return an indeterminate value. 3.5.12 reserved (group 3: apr 16) read/write: r reset value: 0x00 reserved reserved bits [7:0] these bits are reserved for lsi logic internal use only. when read, they will return an indeterminate value. 3.5.13 uc status bytes (group 3: apr 17 to 21) the uc status bytes are user-de?ned. they are cleared on hardware reset and when the microcontroller is disabled. vcr[2:0] de?nition 0 0 0 rate 1/2 0 0 1 rate 2/3 0 1 0 rate 3/4 0 1 1 rate 5/6 1 0 0 rate 6/7 1 0 1 rate 7/8 1 1 0 unused 1 1 1 unused apr d7 d0 15 reserved apr d7 d0 16 reserved L64724tm_300.book page 31 friday, april 14, 2000 2:17 pm
3-32 L64724 registers read/write: r reset value: 0x0000 ucsb0 microcontroller status byte 0 [7:0] ucsb0 is a user-de?ned status byte and can be updated as de?ned in the microcoded instructions of the on-chip microcontroller. ucsb1 microcontroller status byte 1 [7:0] ucsb1 is a user-de?ned status byte and can be updated as de?ned in the microcoded instructions of the on-chip microcontroller. ucsb2 microcontroller status byte 2 [7:0] ucsb2 is a user-de?ned status byte and can be updated as de?ned in the microcoded instructions of the on-chip microcontroller. ucsb3 microcontroller status byte 3 [7:0] ucsb3 is a user-de?ned status byte and can be updated as de?ned in the microcoded instructions of the on-chip microcontroller. ucsb4 microcontroller status byte 4 [7:0] ucsb4 is a user-de?ned status byte and can be updated as de?ned in the microcoded instructions of the on-chip microcontroller. apr d7 d0 17 microcontroller status byte 0, ucsb4[7:0] 18 microcontroller status byte 1, ucsb3[7:0] 19 microcontroller status byte 2, ucsb2[7:0] 20 microcontroller status byte 3, ucsb1[7:0] 21 microcontroller status byte 4, ucsb0[7:0] L64724tm_300.book page 32 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-33 3.5.14 demodulator snr estimate (group 3: apr 22 and 23) read/write: r reset value: 0x0000 when read, the demodulator signal to noise ratio (snr) estimate register presents the value for the demodulator snr estimate. snr is 12 bits long. the lsb is found at apr 22, bit 0, and the msb at apr 23, bit 3. see section 5.7.2.1, phase error estimator, page 5-16 , for additional details on snr[7:0]. 3.6 group 4: con?guration registers although most group 4 registers are 8 bits wide, some are as wide as 24 bits. all accesses are done in 8-bit widths. the address pointer register (apr) is used to access these registers as described in section 3.3, groups 0 and 1: address pointer register. apr d7 d0 22 demod snr estimate, snr[7:0] apr d15 d12 d11 d8 23 reserved demod snr estimate, snr[11:8] L64724tm_300.book page 33 friday, april 14, 2000 2:17 pm
3-34 L64724 registers group 4 registers are not affected by resetthe bit values are random immediately after power-up and retain their last known value after any of the three reset operations as shown in section 3.2, reset and how it affects registers. table 3.5 shows the addresses and ?elds of the group 4 registers. table 3.5 group 4 register map apr [5:0] d7 d6 d5 d4 d3 d2 d1 do 0 set to 1 reserved pll_n[5:0] 1 reserved pll_s[5:0] 2 imq dvb_ dss qb pll_t[4:0] 3 viterbi code rate, vcr[2:0] tei sync2_ mod reserved pll_m[1:0] 4 viterbi max data bit count 1, vmdc1[7:0] 5 viterbi max data bit count 2, vmdc2[7:0], low byte 6 viterbi max data bit count 2, vmdc2[15:8], middle byte 7 viterbi max data bit count 2, vmdc2[23:16], high byte 8 viterbi maximum bit error count[7:0], rate 1/2 9 viterbi maximum bit error count[7:0], rate 2/3 10 viterbi maximum bit error count[7:0], rate 3/4 11 viterbi maximum bit error count[7:0], rate 5/6 12 viterbi maximum bit error count[7:0], rate 6/7 13 viterbi maximum bit error count[7:0], rate 7/8 14 synchronization word[7:0] 15 reserved auto rate reserved imq_en di_ bypass l[1:0] 16 reserved sync status select, sss[1:0] sync states acq, ssa[1:0] sync states track, sst[1:0] 17 reserved of reserved (sheet 1 of 4) L64724tm_300.book page 34 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-35 18 pll_reset 19 df_select[2:0] df_gain[1:0] df_ratio[2:0] 20 reserved pd reserved mf_20_ 35 21 pclk_inv pll_bp lclk_ off clk_div1[4:0] 22 clk_div2[7:0] 23 dc_offset_on_ off[1:0] reserved clk_div2[12:8] 24 pwr_ref[7:0] 25 reserved int_dc pwr_bw[1:0] 26 scale factor for demi, demq, scale[7:0] 27 snr estimator threshold, snr_ths[7:0] 28 carrier loop lambda, car_lambda_sel[3:0] carrier loop mu, car_mu_sel[3:0] 29 carrier phase lock detector threshold, car_lc_thsl[7:0] 30 reserved 31 rs bit/byte select errorout_ invert spi_on_ off reserved 32 carrier synchronizer sweep rate, car_swr[7:0] 33 carrier synchronizer sweep rate, car_swr[15:8] 34 carrier synchronizer upper sweep limit, car_uswl[7:0] 35 carrier synchronizer upper sweep limit, car_uswl[15:8] 36 carrier synchronizer lower sweep limit, car_lswl[7:0] 37 carrier synchronizer lower sweep limit, car_lswl[15:8] table 3.5 group 4 register map (cont.) apr [5:0] d7 d6 d5 d4 d3 d2 d1 do (sheet 2 of 4) L64724tm_300.book page 35 friday, april 14, 2000 2:17 pm
3-36 L64724 registers 38 carrier loop filter initialization, car_lf_init[7:0] 39 carrier loop filter initialization, car_lf_init[15:8] 40 carrier loop filter initialization, car_lf_init[23:16] 41 car_ swp_ swap car_ error_ swap car_ auto_ swp reserved car_ ped_sel car_ open car_sw 42 clock loop lambda, clk_lambda_sel[3:0] clock loop mu, clk_mu_sel[3:0] 43 clock synchronizer sweep rate, clk_swr[7:0] 44 clock synchronizer sweep rate, clk_swr[15:8] 45 clock synchronizer upper sweep limit, clk_uswl[7:0] 46 clock synchronizer upper sweep limit, clk_uswl[15:8] 47 clock synchronizer lower sweep limit, clk_lswl[7:0] 48 clock synchronizer lower sweep limit, clk_lswl[15:8] 49 clock loop bias, clk_bias[7:0] 50 clock loop bias, clk_bias[15:8] 51 clock loop bias, clk_bias[23:16] 52 reserved clock loop bias, clk_bias[30:24] 53 clk_swp _swap clk_ error_ swap clk_ auto_ swp set to 1 agc_ clk_sel reserved clk_ open clk_sw 54 snr_est pwrp_ tri adc_pd fp_ lock_ len pwrp reserved clk_ alpha_ sel 55 adc_bp ob_2c external control output bits, xctr[3:0] demod _rst fec_ rst 56 reserved 57 reserved table 3.5 group 4 register map (cont.) apr [5:0] d7 d6 d5 d4 d3 d2 d1 do (sheet 3 of 4) L64724tm_300.book page 36 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-37 3.6.1 pll parameter n (group 4: apr 0) the pll con?guration parameter n (pll_n[5:0]) con?gures the pll module for clock synthesis. read/write: r/w set to 1 set to 1 7 this is an internal test bit that must be set to 1. reserved reserved 6 this is an internal test bit that must be cleared to 0. 58 reserved 59 serial transmission start data, txsd[6:0] reserved 60 serial transmission data, stxd[7:0] 61 serial transmission end data, txed[7:0] 62 serial_b serial_c[1:0] spi_m[3:0] serial_a 63 fmode spi_clk_ and spi_mod e_a_b re- served spi_n[3:0] 64 spi_gain[7:0](lsb) 65 reserved spi_gain[9:8] 66 spi_bias[7:0] (lsb) 67 spi_bias[15:8] (msb) 68 reserved spi_bias[22:16] 69 timing lock detector threshold, clk_lc_thsl[7:0] table 3.5 group 4 register map (cont.) apr [5:0] d7 d6 d5 d4 d3 d2 d1 do (sheet 4 of 4) apr d7 d6 d5 d0 0 set to 1 reserved pll_n[5:0] L64724tm_300.book page 37 friday, april 14, 2000 2:17 pm
3-38 L64724 registers pll_n pll con?guration parameter n [5:0] pll_n[5:0] is one of four parameters (pll_s, pll_n, pll_t, and pll_m) that you must set to con?gure the pll module for clock synthesis. for more information, see section 4.2, pll clock generation, page 4-3. 3.6.2 pll parameter s (group 4: apr 1) the pll con?guration parameter s (pll_s[5:0]) con?gures the pll module for clock synthesis. read/write: r/w reserved reserved [7:6] the reserved bits are internal test bits that must be cleared to 0. pll_s pll con?guration parameter s [5:0] pll_s[5:0] is one of four parameters (pll_s, pll_n, pll_t, and pll_m) that you must set to con?gure the pll module for clock synthesis. for more information see section 4.2, pll clock generation. 3.6.3 pll parameter t, demodulator and symbol select (group 4: apr 2) the pll con?guration parameter t (pll_t[4:0]) con?gures the pll module for clock synthesis. this register also contains bits to con?gure the demodulator and select the symbol format. read/write: r/w imq (i, -q) symbol format 7 the imq bit indicates the format of the incoming symbol stream. the imq_en bit (apr 15, d3) must be cleared apr d7 d6 d5 d0 1 reserved pll_s[5:0] apr d7 d6 d5 d4 d0 2 imq dvb_dss qb pll_t[4:0] L64724tm_300.book page 38 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-39 to 0 for imq to take effect. when imq_en is set to a 1, imq will be disregarded. dvb_dss dvb/dss mode select 6 the dvb_dss bit indicates the format of the incoming symbol stream. the L64724 supports data stream for- mats that conform to either the digital video broadcast standard (dvb) or the speci?cations for the digital satellite system (dss). note that when dss mode is selected (dvb_dss set to 1), the tei indicator bit (apr 3, d4) must be cleared to 0. qb qpsk/bpsk format select 5 set the qb bit to 1 to specify the format of the incoming symbol stream. the qb bit should be cleared to 0 for systems that input a qpsk symbol pair (i, q) once per clk cycle. the qb bit should be set to 1 for bpsk input (i stream only). pll_t pll con?guration parameter t [4:0] pll_t[4:0] is one of four parameters (pll_s, pll_n, pll_t, and pll_m) that you must set to con?gure the pll module for clock synthesis. for more information, see section 4.2, pll clock generation, page 4-3. allowed values are 1 and all even numbers. imq symbol format 0i,q 1 i,-q dvb_dss symbol format 0 dvb format selected 1 dss format selected qb symbol stream format 0 qpsk 1 bpsk L64724tm_300.book page 39 friday, april 14, 2000 2:17 pm
3-40 L64724 registers 3.6.4 pll parameter m, transport and viterbi code rate select (group 4: apr 3) the pll con?guration parameter m (pll_m[1:0]) con?gures the pll module for clock synthesis. this register also contains bits to set the viterbi decoder module code rate and con?gure the transport error indicator. read/write: r/w vcr viterbi code rate [7:5] set these vcr bits to select the code rate for the L64724 viterbi decoder module. the three bits are assigned as follows: the vcr bits are disregarded when automatic viterbi rate acquisition is selected (auto rate bit: group 4, apr 15, d6 = 1.) tei transport error indicator select 4 when the transport error indicator select bit is set to 1, it activates the transport error indicator mechanism. in this mode, the ?rst bit following the synchronization byte in a transport packet is forced high whenever the reed- solomon decoder ?nds the data block to be uncorrectable. otherwise, it remains unchanged. when the tei bit is cleared to 0, the transport error indicator will not be set at any time (see the mpeg-2 system apr d7 d5 d4 d3 d2 d1 d0 3 viterbi code rate, vcr[2:0] tei sync2_ mod reserved pll_m[1:0] vcr[2:0] de?nition 0 0 0 rate 1/2 0 0 1 rate 2/3 0 1 0 rate 3/4 0 1 1 rate 5/6 1 0 0 rate 6/7 1 0 1 rate 7/8 1 1 0 unused 1 1 1 unused L64724tm_300.book page 40 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-41 speci?cation h.222 transport stream packet layer, para- graph 2.4.3.2). using the tei feature allows a simpler interface to the lsi logic l64007 transport demultiplexer. for more information, see the lsi logic l64007 mpeg-2, dvb, and tsat transport demultiplexer technical manual . sync2_mod sync2 modi?ed 3 the sync2_mod bit selects an alternate method of acquiring sync 2. it should be set to 1 for normal operation. reserved reserved 2 this bit must be cleared to 0 for proper operation. pll_m vco frequency range for pll module [1:0] pll_m is one of four parameters (pll_s, pll_n, pll_t, and pll_m) that you must set to con?gure the pll module for clock synthesis. for more information see section 4.2, pll clock generation, page 4-3. con?gure the pll_m[1:0] bits to tell the L64724 the frequency range of the pll. 3.6.5 viterbi maximum data bit count 1 (group 4: apr 4) this register speci?es the number of valid symbols, divided by 256, over which the number of viterbi decoded symbol errors are counted for synchronization. for example, a value of vmdc1[7:0] = 0x02 speci?es 512 data bits. equation 3.1 pll_m[1:0] pll range 0 0 40C50 mhz 0 1 50C60 mhz 1 0 60C70 mhz 1 1 70C90 mhz vmdc1 symbols 256 ------------------------ - = L64724tm_300.book page 41 friday, april 14, 2000 2:17 pm
3-42 L64724 registers for more information see section 7.1.3, viterbi ber monitor, page 7-7 . read/write: r/w 3.6.6 viterbi max data bit count 2 (group 4: apr 5, 6, and 7) these registers specify the number of valid symbols, divided by four, over which the number of symbol errors in the viterbi output data stream are counted, after synchronization. the symbol error count is then displayed as vberc (group 3, apr 4,5). the value for vmdc2 occupies 24 bits and is arranged as three bytes with apr 5, bit 0 being the least signi?cant bit and apr 7, bit 7 being the most signi?cant bit. for example, a value of vmdc2[23:0] = 0x00.00f0 speci?es 960 data bits. equation 3.2 for more information see section 7.1.3, viterbi ber monitor. read/write: r/w 3.6.7 viterbi maximum bit error count, rate 1/2 (group 4: apr 8) this register speci?es the maximum number of viterbi symbol errors that are allowed to occur within the data period set by vmdc1 (group 4, apr 4) to achieve viterbi module synchronization. apr d7 d0 4 viterbi maximum data bit count 1, vmdc1[7:0] apr d7 d0 5 viterbi maximum data bit count 2, low byte, vmdc2[7:0] apr d15 d8 6 viterbi maximum data bit count 2, middle byte, vmdc2[15:8] apr d23 d16 7 viterbi maximum data bit count 2, high byte, vmdc2[23:16] vmdc2 symbols 4 ------------------------ - = L64724tm_300.book page 42 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-43 note: this register is used during viterbi code rate acquisition for rate 1/2. whenever the symbol error count from the internal bit error counter exceeds the value vmbec_1_2[7:0], the synchronization module concludes that the viterbi decoder module is out of synchronization and proceeds to adjust the phase of the incoming symbol stream until synchronization is reached. the symbol error count is given by equation 3.3 . equation 3.3 for example, a value of vmbec_1_2[7:0] = 0x03 speci?es 416 errors. for more information, see section 7.1.3, viterbi ber monitor, page 7-7. note that a software reset (fec_rst, apr 55, bit 0) does not affect the contents of the register. read/write: r/w 3.6.8 viterbi maximum bit error count, rate 2/3 (group 4: apr 9) this register speci?es the maximum number of viterbi symbol errors that are allowed to occur within the data period set by vmdc1 (group 4, apr 4) to achieve viterbi module synchronization. note: this register is used during viterbi code rate acquisition for rate 2/3. whenever the symbol error count from the internal bit error counter exceeds the value vmbec_2_3[7:0], the synchronization module concludes that the viterbi decoder module is out of synchronization and proceeds to adjust the phase of the incoming symbol stream until synchronization is reached. the symbol error count is given by equation 3.4 . equation 3.4 apr d7 d0 8 viterbi maximum bit error count vmbec_1_2[7:0], rate 1/2 number of symbol errors 128 vmbec_1_2 32 + = number of symbol errors 128 vmbec_2_3 32 + = L64724tm_300.book page 43 friday, april 14, 2000 2:17 pm
3-44 L64724 registers for example, a value of vmbec_2_3[7:0] = 0x03 speci?es 416 errors. for more information, see section 7.1.3, viterbi ber monitor. note that a software reset (fec_rst, apr 55, bit 0 set to 1) does not affect the contents of the register. read/write: r/w 3.6.9 viterbi maximum bit error count, rate 3/4 (group 4: apr 10) this register speci?es the maximum number of viterbi symbol errors that are allowed to occur within the data period set by vmdc1 (group 4, apr 4) to achieve viterbi module synchronization. note: this register is used during viterbi code rate acquisition for rate 3/4. whenever the symbol error count from the internal bit error counter exceeds the value vmbec_3_4[7:0], the synchronization module concludes that the viterbi decoder module is out of synchronization and proceeds to adjust the phase of the incoming symbol stream until synchronization is reached. the symbol error count is given by equation 3.5 . equation 3.5 for example, a value of vmbec_2_3[7:0] = 0b0000.0011 speci?es 416 errors. for more information, see section 7.1.3, viterbi ber monitor, page 7-7 . note that a software reset (fec_rst, apr 55, bit 0 set to 1) does not affect the contents of the register. read/write: r/w apr d7 d0 9 viterbi maximum bit error count vmbec_2_3[7:0], rate 2/3 apr d7 d0 10 viterbi maximum bit error count vmbec_3_4[7:0], rate 3/4 number of symbol errors 128 vmbec_3_4 32 + = L64724tm_300.book page 44 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-45 3.6.10 viterbi maximum bit error count, rate 5/6 (group 4: apr 11) this register speci?es the maximum number of viterbi symbol errors that are allowed to occur within the data period set by vmdc1 (group 4, apr 4) to achieve viterbi module synchronization. note: this register is used during viterbi code rate acquisition for rate 5/6. whenever the symbol error count from the internal bit error counter exceeds the value vmbec_5_6[7:0], the synchronization module concludes that the viterbi decoder module is out of synchronization and proceeds to adjust the phase of the incoming symbol stream until synchronization is reached. the symbol error count is given by equation 3.6 . equation 3.6 for example, a value of vmbec_5_6[7:0] = 0x03 speci?es 416 errors. for more information, see section 7.1.3, viterbi ber monitor, page 7-7. note that a software reset (fec_rst, apr 55, bit 0 set to 1) does not affect the contents of the register. read/write: r/w 3.6.11 viterbi maximum bit error count, rate 6/7 (group 4: apr 12) this register speci?es the maximum number of viterbi symbol errors that are allowed to occur within the data period set by vmdc1 (group 4, apr 4) to achieve viterbi module synchronization. note: this register is used during viterbi code rate acquisition for rate 6/7. whenever the symbol error count from the internal bit error counter exceeds the value vmbec_6_7[7:0], the synchronization module concludes that the viterbi decoder module is out of synchronization and apr d7 d0 11 viterbi maximum bit error count vmbec_5_6[7:0], rate 5/6 number of symbol errors 128 vmbec_5_6 32 + = L64724tm_300.book page 45 friday, april 14, 2000 2:17 pm
3-46 L64724 registers proceeds to adjust the phase of the incoming symbol stream until synchronization is reached. the symbol error count is given by equation 3.7 . equation 3.7 for example, a value of vmbec_6_7[7:0] = 00x03 speci?es 416 errors. for more information, see section 7.1.3, viterbi ber monitor, page 7-7. note that a software reset (fec_rst, apr 55, bit 0 set to 1) does not affect the contents of the register. read/write: r/w 3.6.12 viterbi maximum bit error count, rate 7/8 (group 4: apr 13) this register speci?es the maximum number of viterbi symbol errors that are allowed to occur within the data period set by vmdc1 (group 4, apr 4) to achieve viterbi module synchronization. note: this register is used during viterbi code rate acquisition for rate 7/8. whenever the symbol error count from the internal bit error counter exceeds the value vmbec_7_8[7:0], the synchronization module concludes that the viterbi decoder module is out of synchronization and proceeds to adjust the phase of the incoming symbol stream until synchronization is reached. the symbol error count is given by equation 3.8 . equation 3.8 apr d7 d0 12 viterbi maximum bit error count vmbec_6_7[7:0], rate 6/7 number of symbol errors 128 vmbec_6_7 32 + = number of symbol errors 128 vmbec_7_8 32 + = L64724tm_300.book page 46 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-47 for example, a value of vmbec_7_8[7:0] = 0b0000.0011 speci?es 416 errors. for more information, see section 7.1.3, viterbi ber monitor, page 7-7 . note that a software reset (fec_rst, apr 55, bit 0 set to 1) does not affect the contents of the register. read/write: r/w 3.6.13 synchronization word (group 4: apr 14) this register contains the synchronization word used by the synchronization module in stages two and three. within this byte, the msb is chronologically oldest and the lsb is chronologically newest. see section b.4, qpsk demodulator and fec con?guration example: low data rates, page b-30 , for a typical setting for synchronization word[7:0]. read/write: r/w apr d7 d0 13 viterbi maximum bit error count vmbec_7_8[7:0], rate 7/8 apr d7 d0 14 synchronization word[7:0] L64724tm_300.book page 47 friday, april 14, 2000 2:17 pm
3-48 L64724 registers 3.6.14 mismatching bits in sync 2 tracking mode (group 4: apr 15) this register is used to set the maximum number of mismatching bits allowed to declare a match when comparing the data stream to the reference synchronization word during the tracking phase in the second synchronization stage. read/write: r/w reserved reserved 7 this bit should be cleared to 0 for normal operation. auto rate viterbi decoder automatic rate acquisition 6 the auto rate bit, when set to 1, enables automatic acquisition of the viterbi code rate for the convolutional decoder. when dvb mode is selected (apr 2, d6, dvb_dss = 0) the set of code rates that are being considered for automatic acquisition are 1/2, 2/3, 3/4, 5/6 and 7/8. when dss mode is selected (apr 2, d6, dvb_dss = 1) the rates include 2/3 and 6/7. the vcr bits (apr 3) are disregarded when the auto rate bit is set. the code rate identi?ed by the auto rate mechanism is available under group 3, apr 14 (viterbi coder rate registers). when the auto rate bit is 0, the viterbi code rate is determined by the contents of the vcr ?eld (apr 3). reserved reserved [5:4] the reserved bits are for internal use only. they should always be cleared to 0, and produce random results when read. apr d7 d6 d5 d4 d3 d2 d1 d0 15 reserved auto rate reserved imq_en di_bypass l[1:0] auto rate viterbi decoder acquisition mode 0 code rate determined by vcr[2:0] 1 automatic code rate acquisition L64724tm_300.book page 48 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-49 imq_en (i, -q) format resolution enable 3 when the imq_en bit is set to 1, the synchronization mechanism used for the convolutional decoder automatically resolves phase re?ection (i, -q). in this case, the polarity of the imq bit (apr 2) is disregarded. when the imq_en bit is 0, the imq bit determines the symbol format. di_bypass deinterleaver bypass 2 when set to 1, the di_bypass bit causes the deinter- leaver module to be bypassed. when the bit is 0, the deinterleaver functions according to the dvb or dss speci?cations. l[1:0] mismatching bits, tracking mode, sync2 [1:0] this ?eld is used to set the maximum number of mismatching bits allowed to declare a match when comparing eight bits in the data stream to the reference synchronization word during tracking phase in the second synchronization stage. the l[1:0] bits can be con?gured from 0b00 to 0b10. higher values of l[1:0] result in a smaller probability of loss of lock due to random noise. lower values result in a higher probability of loss. 3.6.15 synchronization states and bclkout format (group 4: apr 16) this register is used to select the algorithms used in the synchronization modules, and which modules synchronization status will be shown on the sync output pin. the register also selects the frequency of the clock that will be output on the bclkout pin. imq_en symbol format 0 determined by the value of imq (apr 2, d7) 1 automatically determined by synchronization mechanism. l[1:0] number of mismatching bits 00 0 01 1 10 2 1 1 illegal value L64724tm_300.book page 49 friday, april 14, 2000 2:17 pm
3-50 L64724 registers read/write: r/w reserved reserved [7:6] the reserved bits must be cleared to 0 for proper operation. sss[1:0] synchronization status/xctr[3] select [5:4] the sss[1:0] bits allow you to observe the synchronization status of one of the three synchronization modules or the xctr[3] output on the xctr[3] output pin. the synchronization modules that may be observed are viterbi decoder synchronization, deinterleaver/reed-solomon decoder synchronization, and descrambler synchronization. program the sss[1:0] ?eld to determine which one of these status bits will be propagated to the xctr[3] pin. note that os[4:0] (group 4, apr 17) should be set to 0b00000. ssa[1:0] synchronization states, acquisition mode [3:2] the second synchronization module (after the viterbi decoder and before the deinterleaver module) allows three different state diagrams to be used in the acquisition phase. the number of properly identi?ed synchronization words that will cause in-synchronization to be declared can be con?gured from 3 to 6. for more apr d7 d6 d5 d4 d3 d2 d1 d0 16 reserved sss [1:0] ssa [1:0] sst [1:0] sss[1:0] xctr[3] pin connection 0 0 viterbi decoder sync 0 1 di/rs decoder sync 1 0 descrambler sync 1 1 xctr[3] (apr 55, d5) L64724tm_300.book page 50 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-51 information, see section 6.3, reed-solomon deinter- leaver synchronization, page 6-8. sst[1:0] synchronization status, tracking mode [1:0] the second synchronization module (after the viterbi decoder and before the deinterleaver module) allows two, three, four, or ?ve misdetected synchronization words before the L64724 declares a loss of synchronization. for more information, see section 6.3, reed-solomon deinterleaver synchronization. 3.6.16 output control (group 4: apr 17) this register is used to con?gure the channel output data path. read/write: r/w reserved reserved [7:6] the reserved bits must be cleared to 0 for proper operation. of descrambler output format 5 writing to the of bit sets the descrambler output mode as shown in the following table. ssa[1:0] number of sync words found to acquire 00 3 01 4 10 5 11 6 sst[1:0] number of missed sync words until loss of lock 00 2 01 3 10 4 11 5 apr d7 d6 d5 d4 d0 17 reserved of reserved L64724tm_300.book page 51 friday, april 14, 2000 2:17 pm
3-52 L64724 registers in serial channel output mode, one bit of decoded data is presented on the co[0] pin every pclk cycle. in parallel channel output mode, one byte of decoded data is presented on the co[7:0] channel data out bus every eight pclk cycles. when serial mode is selected, the bclkout pin is forced low. when the spi_on_off bit (group 4, apr 31, bit 5) is a 1, the of bit is ignored. reserved reserved [4:0] the reserved bits must be set to 0 for proper operation. 3.6.17 pll reset (group 4: apr 18) read/write: write only writing any value to apr 18 generates an internal reset pulse for the pll module. the L64724 ignores any data on the d[7:0] bus during a write to this register. you should reset the pll module before operating it. the pll reset register (apr18) cannot be read. 3.6.18 decimation filter control (group 4: apr 19) read/write: r/w the decimation filter control register sets clock parameters related to the demodulator module carrier synchronization logic. of co[7:0] channel data out 0 serial channel output mode 1 parallel channel output mode apr d7 d0 18 pll_reset apr d7 d5 d4 d3 d2 d0 19 df_select[2:0] df_gain[1:0] df_ratio[2:0] L64724tm_300.book page 52 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-53 df_select[2:0] decimation filter select [7:5] program the df_select[2:0] ?eld to select one of the four ?lters contained in the decimation ?lter module or to bypass the decimation ?lter. df_gain[1:0] decimation filter gain [4:3] the table below indicates the gain of the decimation ?lter. df_ratio[2:0] decimation filter ratio [2:0] program the df_ratio[2:0] ?eld to set the amount of decimation. the value indicates the ratio of outgoing to incoming samples at the decimation ?lter. for more information see section 5.4, decimation filters, page 5-4. df_select[2:0] filter 1 0 0 no filter (bypass) 0 0 0 filter 1 0 0 1 filter 2 0 1 0 filter 3 0 1 1 filter 4 df_gain[1:0] gain factor 00 1 01 2 10 4 11 8 df_ratio[2:0] decimation ratio 100 1 0 0 0 1/2 0 0 1 1/4 0 1 0 1/8 0 1 1 1/16 L64724tm_300.book page 53 friday, april 14, 2000 2:17 pm
3-54 L64724 registers 3.6.19 clock loop control 2 (group 4: apr 20) the clock loop control 2 register sets the matched ?lter roll-off factor, used in the demodulator module pll. the register also contains the power down control bit. read/write: r/w reserved reserved [7:5] these reserved bits must be cleared to 0 for proper operation. pd power down 4 when you set the pd bit to 1, all modules except the asynchronous microprocessor interface are turned off to minimize power consumption. no data processing occurs during power down. when you clear the pd bit to 0, all elements operate. you should apply a reset pulse after you change the pd bit from 1 to 0 (wake-up) before you start processing data. reserved reserved [3:1] these reserved bits must be cleared to 0 for proper operation. mf_20_35 matched filter roll-off factor 0 the mf_20_35 bit, when set to 1, selects a roll-off factor of 0.35 for the matched ?lter in accordance with the dvb speci?cations. when the mf_20_35 bit is 0, a 0.20 roll- off factor is selected for dss systems. apr d7 d5 d4 d3 d1 d0 20 reserved pd reserved mf_20_35 pd de?nition 0 normal operation 1 device in power down mode mf_20_35 matched filter roll-off factor 0 0.20 1 0.35 L64724tm_300.book page 54 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-55 3.6.20 clock divider (group 4: apr 21) this register is used to set the division ratio for the sampling clock. read/write: r/w pclk_inv pclk inversion 7 when the pclk_inv bit is 0, the clock signal generated internally is available on the pclk pin. when the pclk_inv bit is 1, the polarity of the pclk output waveform is inverted. pll_bp pll bypass 6 when the pll_bp bit is 0, the internal pll module is used to generate the clock for the adc, demodulator, and fec modules. when the bit is a 1, the pll module is bypassed and the pclk signal is generated by dividing the frequency of clk by the value of clk_div1. for details, see chapter 4. lclk_off lclk off 5 the lclk_off bit, when 0, turns off the lclk signal. when the lclk_off bit is a 1, the lclk signal is turned on. clk_div1 input division factor for clk [4:0] when the pll module is bypassed (pll_bp = 1), the clk_div1[4:0] field sets the input division factor for the clock signal supplied to the L64724 on the clk pin. the clk_div1[4:0] bits are not used when the pll_bp bit is 0. apr d7 d6 d5 d4 d0 21 pclk_inv pll_bp lclk_off clk_div1[4:0] L64724tm_300.book page 55 friday, april 14, 2000 2:17 pm
3-56 L64724 registers 3.6.21 clock divider 2 (group 4: apr 22, 23) this register is used to set the division ratio for the generation of lclk. read/write: r/w dc_offset_on_off dc offset on off[15:14] the dc_offset_on_off[1:0] bits control the dc offset circuit as shown in the following table. reserved reserved 13 the reserved bit must always be cleared to 0, and produces random results when read. clk_div2 input division factor for lclk [7:0], [12:8] the frequency of the output signal lclk is determined by the value of clk_div2[12:0] as follows: lclk = clk/clk_div2[12:0]. 3.6.22 power reference level (group 4: apr 24) read/write: r/w apr d7 d0 22 clk_div2[7::0] apr d15 d14 d13 d12 d8 23 dc_offset_on_ off[1:0] reserved clk_div2[12:8] dc_offset_ on_off[1] dc_offset_ on_off[0] de?nition 0 x dc_offset off 1 0 dc_offset on; noise feedback off 1 1 dc_offset on; noise feedback on apr d7 d0 24 pwr_ref[7:0] L64724tm_300.book page 56 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-57 this register sets the reference power level for the analog-to-digital converter. for details on setting this register, see section 5.8.1, adc range and power reference, page 5-20 . pwr_ref[7:0] is a positive, unsigned number. 3.6.23 power estimation bandwidth and i/q dc offset (group 4: apr 25) this register is used to enable internal dc offset compensation on the i and q signals and sets the power estimation bandwidth. read/write: r/w reserved reserved [7:3] the reserved bits must always be cleared to 0, and will produce random results when read. int_dc internal dc offset compensation on i and q 2 set the int_dc bit to 1 to enable internal dc offset compensation on the i and q signals at the output of the matched ?lter. pwr_bw power estimation bandwidth [1:0] program the pwr_bw[1:0] bits to set the power estimation bandwidth. for more information see section 5.8.2, power control loop, page 5-21. apr d7 d3 d2 d1 d0 25 reserved int_ dc pwr_bw[1:0] int_dc de?nition 0 disabled 1 enabled pwr_bw[1:0] symbol rate (mhz) 0 0 20C45 0 1 10C20 1 0 5C10 1 1 2C5 L64724tm_300.book page 57 friday, april 14, 2000 2:17 pm
3-58 L64724 registers 3.6.24 scale factor for demi and demq outputs (group 4: apr 26) read/write: r/w program the scale[7:0] bits to set the scale factor for the demi and demq outputs from the demodulator to the fec decoder. for the relationship between scale[7:0] and pwr_ref[7:0], see section 5.9, output control, page 5-22. scale[7:0] is a positive, unsigned number. 3.6.25 snr estimator threshold (group 4: apr 27) read/write: r/w use this register to set the value that the phase detectors signal to noise ratio (snr) comparator uses as a threshold when deciding which gain value to use. for details, see figure 5.7 in section 5.7.2, carrier phase tracking, page 5-16 . snr_ths[7:0] is an unsigned number. 3.6.26 carrier loop filter parameters (group 4: apr 28) read/write: r/w car_lambda_sel[3:0] carrier loop lambda [7:4] program the car_lambda_sel[3:0] ?eld with values that set the parameters of the carrier recovery loop. for details, see section 5.7.2.2, loop characteristics, page 5-17. apr d7 d0 26 scale[7:0] apr d7 d0 27 snr_ths[7:0] apr d7 d4 d3 d0 28 car_lambda_sel[3:0] car_mu_sel[3:0] L64724tm_300.book page 58 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-59 car_mu_sel[3:0] carrier loop mu [3:0] program the car_mu_sel[3:0] ?eld with values that set the parameters of the carrier recovery loop. for details, see section 5.7.2.2, loop characteristics, page 5-17. 3.6.27 carrier phase lock detector threshold (group 4: apr 29) read/write: r/w the car_lc_thsl[7:0] determines the threshold for the carrier phase lock detector. for details, see section 5.7.1.5, phase lock detection, page 5-15 . car_lc_thsl[7:0] is an unsigned number. 3.6.28 reserved (group 4: apr 30) read/write: r/w reserved reserved [7:0] the reserved bits are for lsi logic internal use only and must be cleared to 0. 3.6.29 bit/byte error correct and spi mode control (group 4: apr 31) the following register controls reed solomon bit/byte error count selection and the spi mode selection. read/write: r/w apr d7 d0 29 car_lc_thsl[7:0] apr d7 d0 30 reserved apr d7 d6 d5 d4 d0 31 rs bit/byte_ select errorout_invert spi_on_off reserved L64724tm_300.book page 59 friday, april 14, 2000 2:17 pm
3-60 L64724 registers rs bit/byte_select reed solomon bit/byte select 7 the rs bit/byte_select bit controls the reed-solomon corrected bit error count/byte error count selection. when the bit is 1, reading the group 3 registers (apr0 and apr1) yields the reed-solomon byte error count. when the bit is 0, reading the group 3 registers (apr0 and apr1) yields the reed-solomon bit error count, which is the cec multiplied by eight. errorout_invert errorout signal invert 6 when the error_out_invert bit is 1, the errorout signal polarity is inverted from active-low to active- high. spi_on_off 5 when the spi_on_off bit is set to 1, the spi mode is on. when the bit is 0, the spi mode is off. when setting this bit, bit 4 of apr63 should also be set appropriately to select the spi mode. note: the L64724 revision b only supports modes 2 and 3 of the spi speci?cation, not mode 1. reserved reserved [4:0] these bits are reserved. 3.6.30 carrier synchronizer sweep rate (group 4: apr 32 and 33) read/write: r/w car_swr carrier synchronizer sweep rate [15:0] the car_swr[15:0] value determines the carrier syn- chronizer sweep rate. for details, see section 5.7.1.3, frequency sweep rate, page 5-14. car_swr[15:0] is a signed, twos complement number. apr d7 d0 32 car_swr[7:0] apr d15 d8 33 car_swr[15:8] L64724tm_300.book page 60 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-61 3.6.31 carrier synchronizer sweep upper limit (group 4: apr 34 and 35) the values in the car_uswl[15:0] register set the upper limits of the frequency sweep. for details, see section 5.7.1.1, frequency sweep limits, page 5-13. car_uswl[15:0] is a twos-complement number. read/write: r/w car_uswl carrier sweep upper sweep limit [15:0] program the car_uswl[15:0] bits to set the upper limit of the frequency sweep. 3.6.32 carrier synchronizer sweep lower limit (group 4: apr 36 and 37) program the car_lswl[15:0] register to set the lower limit of the frequency sweep. for details, see section 5.7.1.4, car_swr, page 5-14 . car_lswl[15:0] is a twos-complement number. read/write: r/w car_lswl carrier sweep lower sweep limit [15:0] program the car_lswl[15:0] bits to set the lower limit of the frequency sweep. apr d7 d0 34 car_uswl[7:0] apr d15 d8 35 car_uswl[15:8] apr d7 d0 36 car_lswl[7:0] apr d15 d8 37 car_lswl[15:8] L64724tm_300.book page 61 friday, april 14, 2000 2:17 pm
3-62 L64724 registers 3.6.33 carrier loop filter initialization (group 4: apr 38, 39, and 40) program the car_lf_init[23:0] bits with values that set the content of the carrier loop filter accumulator. for details, see section 5.7.2.2, loop characteristics, page 5-17 . read/write: r/w car_lf_init carrier loop filter init [23:0] program the car_lf_init[23:0] bits to set the value for the accumulator in the loop ?lter of the carrier recovery loop. car_lf_init[23:0] is a twos-complement number. 3.6.34 carrier loop con?guration register (group 4: apr 41) this resister contains the various control bits that con?gure the carrier loop synchronizer loop logic. for more information, see section 5.7, carrier recovery loop, page 5-12. read/write: r/w car_swp_swap swap carrier sweep direction 7 set the car_swp_swap bit to control whether the carrier acquisition frequency sweep direction is normal or reversed. it should be toggled whenever the carrier apr d7 d0 38 car_lf_init[7:0] apr d15 d8 39 car_lf_init[15:8] aprs d23 d16 40 car_lf_init[23:16] apr d7 d6 d5 d4 d3 d2 d1 d0 41 car_swp_ swap car_error_ swap car_auto_ swp reserved car_ped_ sel car_open car_sw L64724tm_300.book page 62 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-63 sweep reaches its limit without achieving carrier lock, or when the constellation has locked at 45 degrees. car_error_swap swap carrier error detector 6 set the car_error_swap bit to control the polarity of the carrier loop error detector (ndaml, ddml). when the bit is 1, the polarity of the detector output is inverted. car_auto_swp automatic carrier sweep control 5 set the car_auto_swp bit to enable automatic control of the carrier sweep mechanism. when the bit is 1, control of the sweep is handled internally. see section 5.6, timing clock recovery, page 5-8 , for more information on carrier sweep. reserved reserved [4:3] the reserved bits are reserved for internal use only. they should always be cleared to 0, and produce random results when read. car_ped_sel carrier phase error detector select 2 program the car_ped_sel bit to select which phase error estimator will be used for carrier phase tracking. for car_swp_swap sweep operation 0 increasing frequency 1 decreasing frequency car_error_swap error detector output 0 normal 1 inverted car_auto_swp sweep mode 0 manual sweep control by user 1 automatic internal sweep control L64724tm_300.book page 63 friday, april 14, 2000 2:17 pm
3-64 L64724 registers details, see section 5.7.2, carrier phase tracking, page 5-16 , and table 5.4 . car_open carrier loop open 1 set the car_open bit to 1 to disable the carrier loop (the carrier loop integrator maintains its current value). when the car_open bit is 0, the carrier loop operates normally. car_sw sweep enable for carrier loop 0 set the car_sw bit to 1 to enable the carrier acquisition sweep generator. for more information see section 5.7.1, carrier acquisition, page 5-13. 3.6.35 clock loop terms (group 4: apr 42) read/write: r/w clk_lambda_sel clock loop lambda [7:4] program the clk_lambda_sel[7:4] bits with values that set the parameters of the clock recovery loop. for details, see section 5.6.1, clock acquisition and track- ing modes, page 5-9. car_ped_sel estimator selected 0 decision directed maximum likelihood (ddml) 1 nondata aided maximum likelihood (ndaml) car_open de?nition 0 enable the carrier loop 1 disable the carrier loop car_sw de?nition 0 sweep mechanism off 1 sweep mechanism on apr d7 d4 d3 d0 42 clk_lambda_sel[7:4] clk_mu_sel[3:0] L64724tm_300.book page 64 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-65 clk_mu_sel clock loop mu [3:0] program the clk_mu_sel[3:0] bits with values that set the parameters of the clock recovery loop. for details, see section 5.6.1, clock acquisition and tracking modes, page 5-9. 3.6.36 clock synchronizer sweep rate (group 4: apr 43 and 44) this register determines the clock synchronizer sweep rate. read/write: r/w clk_swr clock synchronizer sweep rate [15:0] clk_swr[15:0] is a signed, twos complement number. for details, see section 5.6.1.2, timing loop sweep equations and timing loop bias, page 5-11. 3.6.37 clock synchronizer sweep upper limit (group 4: apr 45 and 46) read/write: r/w clk_uswl clock sweep upper sweep limit [15:0] program the clk_uswl[15:0] register to set the upper limit of the frequency sweep. for details, see section 5.6.1.2, timing loop sweep equations and timing loop bias, page 5-11 , clk_uswl[15:0] is a twos complement number. apr d7 d0 43 clk_swr[7:0] apr d15 d8 44 clk_swr[15:8] apr d7 d0 45 clk_uswl[7:0] apr d15 d8 46 clk_uswl[15:8] L64724tm_300.book page 65 friday, april 14, 2000 2:17 pm
3-66 L64724 registers 3.6.38 clock synchronizer sweep lower limit (group 4: apr 47 and 48) read/write: r/w clk_lswl clock sweep lower sweep limit [15:0] program the clk_lswl[15:0] register to set the lower limit of the frequency sweep. for details, see section 5.6.1.1, timing loop sweep limits, page 5-10. clk_lswl[15:0] is a twos-complement number. 3.6.39 clock loop bias (group 4: apr 49 to 52) program the clk_bias[30:0] register with values that set the parameters of the clock recovery loop. for details, see section 5.6.1.2, timing loop sweep equations and timing loop bias, page 5-11. read/write: r/w reserved reserved 31 you must set the reserved bit to 0 for normal operation. apr d7 d0 47 clk_lswl[7:0] apr d15 d8 48 clk_lswl[15:8] apr d7 d0 49 clk_bias[7:0] apr d15 d8 50 clk_bias[15:8] apr d23 d16 51 clk_bias[23:16] apr d30 d24 52 reserved clk_bias[30:24] L64724tm_300.book page 66 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-67 clk_bias clock loop bias [30:0] program the clk_bias registers to set the value for the bias parameter within the clock recovery loop. 3.6.40 clock loop con?guration register (group 4: apr 53) this register contains the various control bits that are used to con?gure the clock synchronizer loop logic. read/write: r/w clk_swp_swap swap clock sweep direction 7 set the clk_swp_swap bit to control whether the clock acquisition frequency sweep direction is normal or reversed. it should be toggled whenever the clock sweep reaches its limit without achieving clock lock. clk_error_swap swap timing error detector 6 set the clk_error_swap bit to control the polarity of the timing error detector. when the bit is set to 1, the polarity of the detector output is inverted. clk_auto_swp automatic timing sweep control 5 set the clk_auto_swp bit to enable automatic control of the timing sweep mechanism. when set to 1, the control of the sweep is handled internally. see apr d7 d6 d5 d4 d3 d2 d1 d0 53 clk_swp_ swap clk_error _swap clk_ auto_ swp set to 1 agc_clk_ sel reserved clk_open clk_sw clk_swp_swap sweep operation 0 increasing frequency 1 decreasing frequency clk_error_ swap error detector output 0 normal 1 inverted L64724tm_300.book page 67 friday, april 14, 2000 2:17 pm
3-68 L64724 registers section 5.6, timing clock recovery, page 5-8 , for more information on timing sweep. set to 1 set to 1 4 this bit must be set to 1 for proper operation. agc_clk_sel sigma-delta clocking select 3 when the agc_clk_sel bit is 1, the sigma-delta module integrates the value continuously at the sampling frequency over all samples. when the bit is 0, the sigma- delta module operates on valid symbols only. reserved reserved 2 this bit is reserved. clk_open clock loop open 1 set the clk_open bit to disable the clock loop. the clock loop integrator maintains its current value. when the bit is 0, the clock loop operates normally. clk_sw sweep enable for clock loop 0 set the clk_sw bit to enable the clock acquisition sweep generator. clk_auto_swp sweep mode 0 manual sweep control by user 1 automatic internal sweep control agc_clk_sel clocking select 0 use valid symbols only 1 all samples used for sigma-delta clk_open de?nition 0 enable the clock loop 1 disable the clock loop clk_sw de?nition 0 sweep mechanism off 1 sweep mechanism on L64724tm_300.book page 68 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-69 3.6.41 demodulator con?guration register (group 4: apr 54) this register contains the control bits that con?gure the L64724 demodulator logic. read/write: r/w snr_est snr estimator on/off 7 the snr_est bit enables or disables the snr estimator circuit. pwrp_tri pwrp signal 3-state control 6 the pwrp_tri bit, when set, forces the pwrp output pin to a 3-state condition. adc_pd ad converter power-down 5 the adc_pd bit, when set to 1, turns off the ad converter module to minimize power consumption. no data processing can occur during power-down. the ad converter operates at full power when the adc_pd bit is 0. when the ad converter experiences a wakeup (adc_pd bit changes from 1 to 0), apply a reset pulse to the L64724 before processing data. apr d7 d6 d5 d4 d3 d2 d1 d0 54 snr_est pwrp_tri adc_pd fp_lock_ len pwrp reserved clk_ alpha_ sel snr_est snr estimator 0 off 1on pwrp_tri pwrp output pin 0 normal 1 3-state acd_pd de?nition 0 adc operates normally 1 adc in power down mode L64724tm_300.book page 69 friday, april 14, 2000 2:17 pm
3-70 L64724 registers fp_lock_len frequency/phase lock detector length 4 the fp_lock_len bit operates in conjunction with the carrier threshold ?eld (group 4, apr 29) to set the phase lock detector estimation period. for details, see section 5.7.1.5, phase lock detection, page 5-15 . pwrp pwrp signal invert 3 the pwrp bit, when set to 1, inverts the polarity of the signal output on the pwrp pin. reserved reserved [2:1] you must set the reserved bits to 0 for normal operation. clk_alpha_sel clock loop coef?cient 0 the clk_alpha_sel bit con?gures the coef?cient value (alpha) for the interpolator structure within the clock recovery loop. when the bit is 0, the value for alpha is 0.43. when the bit is 1, the value for alpha is 0.5. the default value for clk_alpha_sel is 0. 3.6.42 external output control bits and reset register (group 4: apr 55) this register contains the control bits for the xctr_out[3:0] external output pins and the bits that reset the demodulator and fec circuitry. read/write: r/w fp_lock_len estimation period 0 normal (long) 1 short pwrp pwrp output pin 0 normal 1 inverted apr d7 d6 d5 d2 d1 d0 55 adc_bp ob_2c xctr[3:0] demod_ rst fec_ rst L64724tm_300.book page 70 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-71 adc_bp ad converter bypass 7 when the adc_bp bit is 1, the dual ad converter modules are bypassed and the digital input signals for the i and q channel are accepted on the ibypass[5:0] and qbypass[5:0] buses, respectively. when the bit is 0, the ad converters are active and analog input signals are accepted on the ivin and qvin pins. ob_2c input format select 6 when the ob_2c bit is 0, the input signal to the demodulator module is assumed to be in offset-binary format. when the bit is 1, the signal is assumed to be in twos-complement format. for operation using the ad converters (adc_bp = 0) ob_2c should be cleared to 0. when the adc modules are bypassed (adc_bp = 1), either format is acceptable through the ibypass and qbypass buses. xctr external control output bits [5:2] the value of the xctr[3:0] ?eld appears on the external output pins xctr_out[3:0] when the serial_a bit (apr 62) is 0. when the serial_a bit is 1, the internal microcontroller determines the values on the external output pins xctr_out[3:0]. for more information see section 5.10, external controls, page 5-23 , and appendix c, "programming the serializer," . demod_rst qpsk demodulator software reset 1 the L64724 resets the internal datapath and the control modules for the qpsk demodulator when the demod_rst bit is set to 1. the L64724 also resets the demodulator processing unit and state machines to their initial states.the fec decoder module is not affected. the bit does not need to be cleared back to 0 to complete the reset. the L64724 issues a single reset pulse each ob_2c de?nition 0 offset-binary format 1 2s-complement format xctr[3:0] de?nition 0 corresponding output pin = vss 1 corresponding output pin = vdd L64724tm_300.book page 71 friday, april 14, 2000 2:17 pm
3-72 L64724 registers time the microprocessor writes a 1 to this bit. for additional details, see section 3.10, reset effect on register bits, page 3-82 . fec_rst fec decoder software reset 0 the L64724 resets the internal datapath and control modules for the fec portion of the device when the fec_rst bit is set to 1. the L64724 also resets the fec processing unit and state machines to their initial states. the demodulator module is not affected. the bit does not need to be cleared back to 0 to complete the reset. the L64724 issues a single reset pulse each time the microprocessor writes a 1 to this bit. for additional details, see section 3.10, reset effect on register bits. 3.6.43 reserved (group 4: apr 56 to 58) read/write: r reset value: 0x00 reserved reserved bits [7:0] the reserved bits are for internal use only. the apr 56 and 57 bits return a value of 0x00 when read, and apr 58 returns a value of 0x14 when read. demod_reset de?nition 0 no reset 1 L64724 issues a demodulator reset fec_rst de?nition 0 no reset 1 L64724 issues an fec reset apr d7 d0 56 reserved = 0x00 57 reserved - 0x00 58 reserved = 0x14 L64724tm_300.book page 72 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-73 3.6.44 serial interface to tuner, data, and control (group 4: apr 59 to 62) these registers are used to communicate on a serial bus to the tuner using the xctr[3:0] output pins. both the host microprocessor and the on-chip microcontroller can write to the registers. a 390 khz sclk for the serial protocol is generated on-chip by dividing the crystal clock (assumed to be 15 mhz) by 38. the sclk signal is output on the xctr[1] pin. sdata for the serial protocol is output on the xctr[0] pin. when the serial_c bit is a 1, a 3-wire protocol is used to transmit the serialized data on xctr[2:0], with xctr[2] acting as the enable signal. read/write: r/w txsd[6:0] serial transmission start data [7:1] when the apr 59 register is written, the on-chip serializer module generates the start condition on the sclk (xctr[1]) and sdata (xctr[0]) pins, serializes and transmits the address in txsd[7:1] (msb ?rst), and appends a r/w bit of 0 to indicate a write cycle to the tuner. stxd[7:0] serial transmission data [7:0] when the apr 60 register is written, the stxd[7:0] data is serialized and transmitted as the next data byte. the ?rst bit sent serially is the msb, bit 7. this register is buffered by the serializer so that a second 8-bit data byte can be loaded into stxd before waiting for the previous byte to be serialized. for a detailed description of the cycles, please refer to appendix c programming the serializer. apr d7 d6 d5 d4 d1 d0 59 serial transmission start data, txsd[6:0] reserved 60 serial transmission data, stxd[7:0] 61 serial transmission end data, txed[7:0] 62 serial_b serial_c[1:0] spi_m[3:0] serial_a L64724tm_300.book page 73 friday, april 14, 2000 2:17 pm
3-74 L64724 registers txed[7:0] serial transmission end data [7:0] when the apr 61 register is written, the txed[7:0] bits are serialized and transmitted as the last serial data byte, and a stop condition is generated on the sdata (xctr[0]) and sclk (xctr[1]) pins. serial_b serial transmission control bit b 7 the serial_b bit indicates whether the host microprocessor or on-chip microcontroller controls the xctr[2:0] pins. when the bit is 1, the on-chip microcontroller controls the xctr[2:0] pins. when the bit is 0, the host microprocessor controls the pins. serial_c[1:0] serial transmission control bit c [6:5] the serial_c[1:0] bits control whether the data is serialized with a serial 2-wire or 3-wire protocol. these bits are used to serialize data, as shown in the table below: for more details, see appendix c programming the serializer. spi_m[3:0] spi_m [4:1] the spi_m[3:0] bits contain the value of the denominator for the viterbi code rate. serial_a serial transmission control bit a 0 the serial_a bit indicates whether the output pins xctr_out[3:0] are to be controlled directly as programmed in the group 4 apr 55 register external control output bits, xctr[3:0], or by the serializer module with data from the txsd, stxd, and txed registers. when the bit is 0 (the default), it indicates that control is as dictated by xctr[3:0]. serial_c[1:0] selected function 0 0 serial 2-wire interface 0 1 3-wire interface, enable high for all valid data 1 0 3-wire interface, enable high for 1 clock cycle at the start of data transfer 1 1 3-wire interface, enable high for 1 clock cycle at the end of data transfer L64724tm_300.book page 74 friday, april 14, 2000 2:17 pm
group 4: con?guration registers 3-75 3.6.45 fmode, spi_clk_and, spi_mode_a_b, and spi_n (group 4: apr 63) this register is used to con?gure the spi interface. fmode bclk format 7 when the fmode bit is 1, the descrambler byte clock signal (bclkout) is enabled during the reed-solomon check bytes. when the bit is 0, the bclkout signal is disabled during check bytes. enabling spi (by setting the spi_on_off bit to 1) automatically takes care of setting the proper values for the fmode bit. the spi_on_off bit is located in group 4, apr 31. spi_clk_and spi_clock anding 6 when the spi_clk_and bit is 1, the spi byte clock is logically anded with the dvalidout signal. spi_mode_a_b spi mode select5 the spi_mode_a_b bit selects between spi mode a (similar to spi speci?cation mode 2), and spi mode b (similar to spi speci?cation mode 3). when the bit is 0, mode a is selected. when the bit is 1, mode b is selected. reserved reserved 4 this bit is reserved for lsi logic and must be cleared to 0. spi_n spi_n [3:0] the spi_n[3:0] bits contain the numerator of the viterbi code rate. apr d7 d6 d5 d4 d3 d0 63 fmode spi_clk _and spi_mode _a_b reserved spi_n[3:0] L64724tm_300.book page 75 friday, april 14, 2000 2:17 pm
3-76 L64724 registers 3.6.46 spi_gain[9:0] (group 4: apr 64 and 65) this register sets the gain of the spi byte clock generation loop. read/write: r/w the spi_gain[9:0] value is used to control the loop gain in the spi byte clock generation module. typical values are 100 for high data rates (no decimation and decimation by 2), 50 for decimation by 4, 25 for decimation by 8, and 10 for decimation by 16. 3.6.47 spi_bias (group 4: apr 66, 67, and 68) this register sets the bias of the spi byte clock generation loop. read/write: r/w this 23-bit value is determined by equation 3.9 . the value must be rounded to the closest integer. equation 3.9 the terms in equation 3.9 have the following meanings: bias = spi_bias[22:0] vcr = viterbi code rate apr d7 d2 d1 d0 64 spi_gain[7:0] apr d15 d10 d9 d8 65 reserved spi_gain[9:8] apr d7 d0 66 spi_bias[7:0] apr d15 d8 67 spi_bias[15:8] apr d23 d22 d16 68 reserved spi_bias[22:16] bias 2 24 vcr f symbol f sample ---------------------------------------------------- - = L64724tm_300.book page 76 friday, april 14, 2000 2:17 pm
group 5: self-tuning microcontroller registers 3-77 f symbol = symbol clock frequency f sample = sampling clock frequency 3.6.48 timing lock detector threshold (group 4: apr 69) this register contains the control bits for the timing lock detector threshold. read/write: r/w clk_lc_thsl[7:0] timing lock detector threshold select [7:0] program these bits to select the threshold values for the timing lock detector mechanism. 3.7 group 5: self-tuning microcontroller registers group 5 contains the memory space for instructions and con?guration for the microprogrammed controller (uc). the registers can be accessed through the chip-level serial or parallel interface 1 . note: these registers are write-only and the internal scratch pad registers are not visible to the host microprocessor. table 3.6 shows the addresses and ?elds of the group 5 registers. apr d7 d0 69 timing lock detector threshold, clk_lc_thsl[7:0] 1. serial mode is the recommended interface mode. lsi logic does not recommend parallel mode for new designs. table 3.6 group 5 register map apr d7 d6 d5 d4 d3 d2 d1 d0 0 uc-instruction 0 [7:0] 1 unused uc instruction 0 [11:8] (sheet 1 of 2) L64724tm_300.book page 77 friday, april 14, 2000 2:17 pm
3-78 L64724 registers 2 uc-instruction 1 [7:0] 3 unused uc instruction 1 [11:8] . . . 510 uc-instruction 255 [7:0] 511 unused uc instruction 255 [11:8] 512 reserved 513 reserved 514 reserved 515 reserved 516 reserved 517 reserved 518 reserved 519 reserved 520 uc con?guration [4:0] arbitra- tion_on reset_ mode micro_ enable table 3.6 group 5 register map (cont.) apr d7 d6 d5 d4 d3 d2 d1 d0 (sheet 2 of 2) L64724tm_300.book page 78 friday, april 14, 2000 2:17 pm
group 5: self-tuning microcontroller registers 3-79 3.7.1 microcontroller instructions (group 5: 0 to 511) the ?rst 512 locations in group 5 (0C511) are occupied by microinstructions for the demodulator control module. each 12-bit microinstruction is distributed over two address locations of the apr. read/write: w the value of n ranges from 0 to 510. 3.7.2 reserved (group 5: apr 512 to 519) apr 512 to 519 are reserved for lsi logic internal use only. they must be cleared to 0. read/write: w reset value: 0x00 apr d7 d0 n microinstruction n/2 [7:0] apr d15 d12 d11 d8 n+1 unused microinstruction n/2 [11:8] apr d7 d0 512 reserved 513 reserved 514 reserved 515 reserved 516 reserved 517 reserved 518 reserved 519 reserved L64724tm_300.book page 79 friday, april 14, 2000 2:17 pm
3-80 L64724 registers 3.7.3 microcontrol enable and con?guration (group 5:apr 520) apr 520 contains the enable and con?guration mechanism for the microcontroller. read/write: w reset value: 0x00 uc con?guration[4:0] microcontrol con?guration [7:3] when a particular bit in the uc con?guration ?eld is set to 1 or 0, it can be used to enable or disable, respectively, portions of the ?ow chart implemented in the microcontroller program. see section b.1, L64724 qpsk demodulator acquisition and debugging tips, page b-1 , for a sample ?owchart. arbitration_on arbitration on 2 when the arbitration_on bit is 1, host microprocessor accesses to the L64724 status and con?guration registers (groups 0 to 5) are allowed while the on-chip uc is running. the host can thus disable the uc by writing into the micro_enable bit while the uc is running. when the arbitration_on bit is 0, host up accesses to the L64724 status and con?guration registers (groups 0 to 5) are not allowed while the on-chip uc is running. the host can then disable the uc when it is running only by writing into group 7 (a[2:0] = 0b111). for more details, see the group 7 registers description. reset_mode reset mode 1 when the reset_mode bit is 1, the uc does not reset its instruction pointer to 0 when disabled while running, and resumes at the instruction it was last decoding when enabled again. when the bit is 0, the uc resets its instruction pointer to 0 on being disabled. it also resets all internal scratch pad registers, uc_status registers (group 3, apr 17 to 21), and associated interrupt bits. apr d7 d3 d2 d1 d0 520 uc con?guration [4:0] arbitration _on reset_ mode micro_ enable L64724tm_300.book page 80 friday, april 14, 2000 2:17 pm
group 6: reserved (internal use only) 3-81 micro_enable demodulator micro control enable 0 when the micro_enable bit is 1, the L64724 internal microcontroller for the demodulator section starts operation. in this mode, the demodulator acquires synchronization for carrier and symbol timing without the intervention of the external microprocessor. when the bit is 0, the microcontrol unit in the demodulator is disabled and the acquisition operation must be performed through the serial or parallel microprocessor interface 1 . 3.8 group 6: reserved (internal use only) 3.9 group 7: arbiter control register group 7 contains the memory space for internal control of the microcontroller/microprocessor arbitration module. apr 0 contains the microcontroller disable mechanism. read/write: r reset value: 0x00 microcontroller disable [7:0] a write operation to group 7 disables the on-chip microcontroller when it is running. a group 7 write can be used if the microcontroller/host microprocessor arbitration register is disabled, which means that host 1. serial mode is the recommended interface mode. lsi logic does not recommend parallel mode for new designs. micro_ enable de?nition 0 microcontroller disabled. acquisition through microprocessor interface. 1 microcontroller enabled. automatic internal demodulator acquisition. apr d7 d0 0 microcontroller disable L64724tm_300.book page 81 friday, april 14, 2000 2:17 pm
3-82 L64724 registers microprocessor write operations to groups 0 to 6 are disallowed while the on-chip microcontroller is enabled. the operation can be described as follows: at power-up the micro_enable (group 5, apr 520) bit is cleared to 0. the external microprocessor loads register groups 2 and 4, then loads the micro instructions into group 5. at this point, the micro_enable bit in group 5 is set to 1. if the uc con?guration[2] bit is cleared to 0 (indicating that arbitration is turned off), further host microprocessor writes to the uc con?guration and micro_enable bits in group 5 are not allowed while the on-chip microcontroller is running. the host microprocessor then shuts off the on-chip microcontroller by writing to group 7. if the uc con?guration[2] bit is set to 1 (indicating that arbitration is turned on), further host microprocessor writes to all register groups are allowed, and the host microprocessor can disable the microcontroller by writing either to group 7 or to the micro_enable bit in group 5. 3.10 reset effect on register bits this section contains a summary table showing how various reset operations affect the L64724 register bits. the following reset operation abbreviations appear in the table: hrChardware reset through the L64724 reset pin. sfCsoftware reset for the fec module (fec_rst bit). sdCsoftware reset for the demodulator module (demod_rst bit) urCmicrocontroller reset based on the falling edge of the micro_enable bit (group 5, apr 520), with the reset mode bit (group 5, apr 520) cleared to 0. nrCnot affected by any reset. L64724tm_300.book page 82 friday, april 14, 2000 2:17 pm
reset effect on register bits 3-83 table 3.7 reset map group apr name d7 d6 d5 d4 d3 d2 d1 d0 0 0 apr0 nr (all bits) 1 0 apr1 nr (all bits) 2 0 smr/ sts hr, sf (all bits) 1 hr, sd (all bits) 2 hr, sd (all bits) 3 hr, ur (all bits) 3 0C5 status hr, sf for all bits of apr 0C5 6 hr, sd nr not used nr 7C10 hr, sd (all bits) 11 hr, sf hr, ur hr, sd hr, sf 12 not used nr nr nr nr nr nr 13 not used nr nr nr nr nr nr 14 not used nr nr hr, sf 15 hr, sf (all bits) 16 hr, sf (all bits) 17 ur (all bits) 18 19 20 21 22 hr, sd (all bits) 23 not used hr, sd (all bits) (sheet 1 of 2) L64724tm_300.book page 83 friday, april 14, 2000 2:17 pm
3-84 L64724 registers 3.11 internal data path reset effects hardware reset through the L64724 reset pin (hr) and software reset for the demodulator module (sd) affect the demodulator. hr and software reset for the fec module (sr) affect the fec module. 4 0C69 config nr (all bits) 50C 511 micro control nr (all bits) 512C 519 hr (all bits) 520 hr hr or group 7 access 6 reserved 7 hr (all bits) table 3.7 reset map (cont.) group apr name d7 d6 d5 d4 d3 d2 d1 d0 (sheet 2 of 2) L64724tm_300.book page 84 friday, april 14, 2000 2:17 pm
L64724 satellite receiver 4-1 chapter 4 channel interfaces and data control the L64724 interface supports two independent interfaces for incoming channel data and for decoded output data. both interfaces are used simultaneously. the input interface transfers data from an external device to the L64724s internal adc module. the output interface transfers data from the L64724 to the next processing device, typically an mpeg-2 transport demultiplexer such as the lsi logic l64007/8. this chapter contains the following sections: section 4.1, data control and clocking schemes section 4.2, pll clock generation section 4.3, data path input interface section 4.4, data output interface L64724tm_300.book page 1 friday, april 14, 2000 2:17 pm
4-2 channel interfaces and data control 4.1 data control and clocking schemes the L64724 uses the clk input clock signal to accommodate a number of possible con?gurations in a channel decoding system. an external crystal oscillator generates the clk signal. an on-chip pll derives the pclk sampling signal from the clk signal. the pclk signal operates the adc, demodulator, and fec modules. lclk is generated by dividing the clk signal by the clk_div parameter. note that due to the demodulator architecture chosen, the output data stream always exhibits a certain degree of burstiness. figure 4.1 L64724 clocking: internal pll osc ivin qvin clk demodulator fec demi demq lclk pll pclk clk_div2 pclk L64724 adc L64724tm_300.book page 2 friday, april 14, 2000 2:17 pm
pll clock generation 4-3 4.2 pll clock generation the data control and clocking schemes presented in section 4.1, data control and clocking schemes, page 4-2 , outline the requirements for the generation of the external clk signal required by the L64724. the internal pll generates the appropriate internal clock signal (pclk) to operate the adc, demodulator, and fec modules. the following clock naming conventions are used in this section: clkCinput clock supplied to L64724 pclkCsampling clock used to operate the adc, demodulator, and fec modules. the on-chip pll derives the pclk signal from the clk signal. lclkCclock generated by dividing the clk input signal by the clk_div2 value. the L64724 contains a clock synthesizer to derive pclk from clk. pclk operates in the range of up to 90 mhz (see figure 4.2 ). a common scenario calls for the connection of a 15 or 60 mhz external signal to the clk pin as the basis for the internal pll clock generation. it is also possible to reuse the 4 mhz tuner crystal for L64724 clock generation purposes. the pll can be con?gured to handle clock ratios for all data rates up to 45 mbaud. the following registers must be set to derive the appropriate clock frequencies: pll_t[4:0] (group 4, apr 2) pll_n[5:0] (group 4, apr 0) pll_s[5:0] (group 4, apr 1) pll_m[1:0] (group 4, apr 3) lclk is derived from clk as shown in equation 4.1 . equation 4.1 lclk clk clkdiv 2 --------------------------- = L64724tm_300.book page 3 friday, april 14, 2000 2:17 pm
4-4 channel interfaces and data control the appropriate pclk frequency is derived from clk based on the symbol rate of the underlying data stream and the viterbi decoder rate chosen. due to the presence of an interpolator within the demodulator module, pclk will be slightly higher in frequency than the average sampling rate for the demodulated symbol stream. based on the assumption that a 15 mhz external clock is available and that the system data rate is chosen at 26 mbaud, a sample calculation for the L64724 clocking scheme is given in the following steps: 1. determine the minimum pclk required. based on the data rate of 26 mbaud, a pclk frequency of at least 52 mhz must be generated. 2. determine pll_t, pll_s, pll_m and pll_n from table 4.1 for the clk rate of 15 mhz. one acceptable set of values, for example, is pll_s = 14, pll_n = 1, pll_t = 4, and pll_m = 1. figure 4.2 pll clock synthesis clk pclk 1/(pll_n) internal lp2 1/(pll_t) 1/(pll_s) pllagnd pllvss pllvdd external loop filter pll_m r c1 c2 pll module externally generated signal note: r = 200 w c1=10nf c2=20pf L64724tm_300.book page 4 friday, april 14, 2000 2:17 pm
pll clock generation 4-5 the example values for pll_s, pll_n, pll_t, and pll_m to cover the frequency range from 2 to 90 mhz for pclk based on a 15 mhz external source and a 4 mhz source are tabulated in table 4.1 and table 4.2 . the formula used for these tables is shown in equation 4.2 . equation 4.2 the pll_m value selects the minimum and maximum vco range. table 4.1 parameters for crystal clock (clk) = 15 mhz pll_s [5:0] pll_n [5:0] pll_t [4:0] pll_m [1:0] vco (min) vco (max) pclk 12 1 2 3 70 90 90.00 58 1 10 3 70 90 87.00 46 1 8 3 70 90 86.25 34 1 6 3 70 85 85.00 56 1 10 3 70 85 84.00 22 1 4 3 70 85 82.50 54 1 10 3 70 85 81.00 32 1 6 3 70 85 80.00 42 1 8 3 70 85 78.75 62 1 12 3 70 85 77.50 10 1 2 3 70 85 75.00 58 1 12 3 70 85 72.50 38 1 8 3 70 85 71.25 28 1 6 2 60 70 70.00 46 1 10 2 60 70 69.00 18 1 4 2 60 70 67.50 (sheet 1 of 4) fpclk fxtal pll_s pll_n pll_t ----------------------------------------- - = L64724tm_300.book page 5 friday, april 14, 2000 2:17 pm
4-6 channel interfaces and data control 44 1 10 2 60 70 66.00 26 1 6 2 60 70 65.00 34 1 8 2 60 70 63.75 50 1 12 2 60 70 62.50 41115060 60.00 46 1 12 1 50 60 57.50 30 1 8 1 50 60 56.25 22 1 6 1 50 60 55.00 36 1 10 1 50 60 54.00 14 1 4 1 50 60 52.50 48 1 14 1 50 60 51.43 20 1 6 0 40 50 50.00 26 1 8 0 40 50 48.75 38 1 12 0 40 50 47.50 61204050 45.00 34 1 12 0 40 50 42.50 22 1 8 0 40 50 41.25 38 1 14 0 40 50 40.71 42 2 8 3 70 85 39.38 62 2 12 3 70 85 38.75 10 2 2 3 70 85 37.50 58 2 12 3 70 85 36.25 38 2 8 3 70 85 35.62 table 4.1 parameters for crystal clock (clk) = 15 mhz (cont.) pll_s [5:0] pll_n [5:0] pll_t [4:0] pll_m [1:0] vco (min) vco (max) pclk (sheet 2 of 4) L64724tm_300.book page 6 friday, april 14, 2000 2:17 pm
pll clock generation 4-7 46 2 10 2 60 70 34.50 18 2 4 2 60 70 33.75 26 2 6 2 60 70 32.50 34 2 8 2 60 70 31.88 42115060 30.00 46 2 12 1 50 60 28.75 22 2 6 1 50 60 27.50 14 2 4 1 50 60 26.25 48 2 14 1 50 60 25.71 26 2 8 0 40 50 24.38 38 2 12 0 40 50 23.75 62204050 22.50 34 2 12 0 40 50 21.25 22 2 8 0 40 50 20.62 42 4 8 3 70 85 19.69 10 4 2 3 70 85 18.75 38 4 8 3 70 85 17.81 18 4 4 2 60 70 16.88 34 4 8 2 60 70 15.94 46 4 12 1 50 60 14.38 22 4 6 1 50 60 13.75 62 6 12 3 70 85 12.92 38 4 12 0 40 50 11.88 table 4.1 parameters for crystal clock (clk) = 15 mhz (cont.) pll_s [5:0] pll_n [5:0] pll_t [4:0] pll_m [1:0] vco (min) vco (max) pclk (sheet 3 of 4) L64724tm_300.book page 7 friday, april 14, 2000 2:17 pm
4-8 channel interfaces and data control 26 6 6 2 60 70 10.83 42 8 8 3 70 85 9.84 38 8 8 3 70 85 8.91 34 8 8 2 60 70 7.97 46 10 10 2 60 70 6.90 38 8 12 0 40 50 5.94 46 14 10 2 60 70 4.93 34 16 8 2 60 70 3.98 62 26 12 3 70 85 2.98 18 34 4 2 60 70 1.99 38 48 12 0 40 50 0.99 table 4.2 parameters for crystal clock (clk) = 4 mhz pll_s [5:0] pll_n [5:0] pll_t [4:0] pll_m [1:0] vco (min) vco (max) pclk 45 1 2 3 70 90 90.00 22 1 1 3 70 90 88.00 43 1 2 3 70 90 86.00 42 1 2 3 70 90 84.00 41 1 2 3 70 90 82.00 20 1 1 3 70 90 80.00 39 1 2 3 70 90 78.00 (sheet 1 of 4) table 4.1 parameters for crystal clock (clk) = 15 mhz (cont.) pll_s [5:0] pll_n [5:0] pll_t [4:0] pll_m [1:0] vco (min) vco (max) pclk (sheet 4 of 4) L64724tm_300.book page 8 friday, april 14, 2000 2:17 pm
pll clock generation 4-9 38 1 2 3 70 90 76.00 37 1 2 3 70 90 74.00 18 1 1 3 70 90 72.00 35 1 2 2 60 70 70.00 34 1 2 2 60 70 68.00 33 1 2 2 60 70 66.00 16 1 1 2 60 70 64.00 31 1 2 2 60 70 62.00 30 1 2 1 50 60 60.00 29 1 2 1 50 60 58.00 14 1 1 1 50 60 56.00 27 1 2 1 50 60 54.00 26 1 2 1 50 60 52.00 25 1 2 0 40 50 50.00 12 1 1 0 40 50 48.00 23 1 2 0 40 50 46.00 45 2 2 3 70 90 45.00 22 1 2 0 40 50 44.00 43 2 2 3 70 90 43.00 42 2 2 3 70 90 42.00 41 2 2 3 70 90 41.00 10 1 1 0 40 50 40.00 39 2 2 3 70 90 39.00 table 4.2 parameters for crystal clock (clk) = 4 mhz (cont.) pll_s [5:0] pll_n [5:0] pll_t [4:0] pll_m [1:0] vco (min) vco (max) pclk (sheet 2 of 4) L64724tm_300.book page 9 friday, april 14, 2000 2:17 pm
4-10 channel interfaces and data control 38 2 2 3 70 90 38.00 37 2 2 3 70 90 37.00 18 2 1 3 70 90 36.00 35 2 2 2 60 70 35.00 34 2 2 2 60 70 34.00 33 2 2 2 60 70 33.00 16 2 1 2 60 70 32.00 31 2 2 2 60 70 31.00 30 2 2 1 50 60 30.00 29 2 2 1 50 60 29.00 14 2 1 1 50 60 28.00 27 2 2 1 50 60 27.00 26 2 2 1 50 60 26.00 25 2 2 0 40 50 25.00 12 2 1 0 40 50 24.00 23 2 2 0 40 50 23.00 22 2 2 0 40 50 22.00 42 4 2 3 70 90 21.00 10 2 1 0 40 50 20.00 38 4 2 3 70 90 19.00 18 4 1 3 70 90 18.00 34 4 2 2 60 70 17.00 16 4 1 2 60 70 16.00 table 4.2 parameters for crystal clock (clk) = 4 mhz (cont.) pll_s [5:0] pll_n [5:0] pll_t [4:0] pll_m [1:0] vco (min) vco (max) pclk (sheet 3 of 4) L64724tm_300.book page 10 friday, april 14, 2000 2:17 pm
pll clock generation 4-11 30 4 2 1 50 60 15.00 22 6 1 3 70 90 14.67 20 6 1 3 70 90 13.33 38 6 2 3 70 90 12.67 34 6 2 2 60 70 11.33 16 6 1 2 60 70 10.67 38 8 2 3 70 90 9.50 22 10 1 3 70 90 8.80 38 10 2 3 70 90 7.60 34 10 2 2 60 70 6.80 20 14 1 3 70 90 5.71 22 18 1 3 70 90 4.89 42 22 2 3 70 90 3.82 22 30 1 3 70 90 2.93 22 46 1 3 70 90 1.91 14 58 1 1 50 60 0.97 table 4.2 parameters for crystal clock (clk) = 4 mhz (cont.) pll_s [5:0] pll_n [5:0] pll_t [4:0] pll_m [1:0] vco (min) vco (max) pclk (sheet 4 of 4) L64724tm_300.book page 11 friday, april 14, 2000 2:17 pm
4-12 channel interfaces and data control 4.3 data path input interface the L64724 provides a mechanism to select the input data path con?gurations. figure 4.3 shows the internal blocks in the decoding pipeline. figure 4.3 L64724 functional blocks in the decoding pipeline the user can select one of two datapath options: no adc bypass bypass adc to select an input con?guration, the external microcontroller must set the input selector adc_bp (group 4, apr 55, bit 7) to enable the appropriate functional blocks. see the description for adc_bp in chapter 3 for details. demodulator section section ivin adc qvin i/qbypass con?guration decoder parameters datapath control fec section adc_bp L64724tm_300.book page 12 friday, april 14, 2000 2:17 pm
data path input interface 4-13 4.3.1 adc, demodulator, and fec active you can supply data to the adc modules and the subsequent demodulator and fec sections by clearing the adc_bp bit to 0. figure 4.4 shows the channel analog data input signals ivin and qvin as well as the input signal clk used in this input con?guration. figure 4.4 clk and analog inputs for channel data input 4.3.2 adc bypassed with demodulator and fec active setting the adc_bp bit to 1 bypasses the adc and supplies data directly to the demodulator section. figure 4.5 shows the channel digital input signals ibypass[5:0] and qbypass[5:0] as well as the pll- generated signal pclk used in this input con?guration. figure 4.5 clk and digital inputs for adc bypass mode table 4.3 input con?guration adc_bp (apr 55, bit 7) input mode chosen 0 adc, demod and fec sections active 1 demod and fec sections active, adc bypassed clk ivin, qvin time ibypass[5:0] qbypass[5:0) pclk L64724tm_300.book page 13 friday, april 14, 2000 2:17 pm
4-14 channel interfaces and data control 4.4 data output interface the L64724 provides a mechanism to observe different outputs of the decoding pipeline. this feature simpli?es performance characterization and system diagnostics tasks. figure 4.3 shows the functional blocks in the decoding pipeline. the user can observe the outputs from the descrambler and the parallel interface module through the co[7:0], dvalidout, erroroutn, fstartout, and bclkout output signals. to select an output, the external microcontroller must set the following output selector bits in group 4: spi_on_off, spi_mode_a_b, spi_clk_and, and of. these bits enable the appropriate functionality, as shown in table 4.4 and figure 4.6 . table 4.4 output selection spi_on _off spi_mode_ a_b spi_clk_ and of functionality chosen 0 x x 0 descrambler serial output; 0 x x 1 descrambler parallel output (bclkout is a data strobe) 1 0 0 x descrambler parallel output (mode a) 1 0 1 x descrambler parallel output (mode a, bclkout anded with dvalidout 1 1 0 x descrambler parallel output (mode b) 1 1 1 x descrambler parallel output (mode b, bclkout anded with dvalidout) L64724tm_300.book page 14 friday, april 14, 2000 2:17 pm
data output interface 4-15 figure 4.6 parallel output interface waveforms 4.4.1 parallel output interface (spi_on_off = 1) 1 you can observe the output of the entire decoding pipeline in parallel format. two main modes exist, determined by the spi_on_off con?guration bit in group 4, apr 31, d5. when the spi_on_off bit is set to 1, the parallel output interface outputs data on co[7:0] in formats that are similar to the speci?cations for the synchronous parallel interface (spi). the parallel outputs are available in two modes, mode a and mode b. in mode a, which is similar to mode 2 of spi, the dvalidout signal is high only during the data bytes and goes low during the rs check bytes. in mode b, which is similar to the spi mode 3, the dvalidout signal always stays high. the fstartout strobe signal overlaps the ?rst data byte. when the spi_on_off bit is high, an internal clock generation scheme guarantees exactly 204 byte clock cycles per packet on the bclkout pin as required for the dvb frame format. this ensures that the data stream is devoid of any gaps within a packet boundary and also between packet boundaries. the data is available on the co[7:0] pins as a continuous ?ow. the L64724 asserts the bclkout signal in the middle of the decoded data bytes, so the device that receives the output from the L64724 can latch data at the bclkout rate instead of at the pclk rate. 1. serial mode is the recommended interface mode. lsi logic does not recommend parallel mode for new designs. bclkout fstartout dvalidout erroroutn n = code word length message co[7:0] dvalidout (mode a) (mode b) byte 0 byte1 byte 2 byte check bytes byte 0 L64724tm_300.book page 15 friday, april 14, 2000 2:17 pm
4-16 channel interfaces and data control 4.4.2 parallel output interface (spi_on_off = 0) when the spi_on_off bit is 0 and the of bit is 1, the L64724 outputs one new data byte on the co[7:0] pins every eight pclk cycles, as shown in figure 4.7 . figure 4.7 descrambler parallel output waveforms the fstartout signal strobe overlaps the ?rst data byte. the L64724 provides the bclkout signal as an additional strobe that has one rising and one falling edge per valid co[7:0] data byte. the L64724 asserts the bclkout signal in the middle of the decoded data bytes, so the device that receives the output from the L64724 can latch data at the bclkout rate instead of at the pclk rate. note that due to the use of a constant sampling frequency and the internal demodulator architecture, the output data stream in the parallel output interface mode contains gaps (when dvalidout is low.) the distribution and position in time of the gaps are governed mainly by the ratio of sampling frequency and symbol rate chosen. gaps can occur at any time in the output data stream. 4.4.3 serial output interface to observe the output of the entire decoding pipeline in serial format, clear the spi_on_off and of con?guration bits to 0. when the of bit (group 4, apr 17) is 0 (serial channel output mode), the L64724 outputs data bit serially on the co[0] pin, as shown in figure 4.8 . bclkout fstartout co[7:0] dvalidout erroroutn message byte 0 byte1 byte 2 check bytes message gap n = code word length L64724tm_300.book page 16 friday, april 14, 2000 2:17 pm
data output interface 4-17 figure 4.8 descrambler serial output waveforms the L64724 outputs one new data bit each pclk cycle. the L64724 asserts the fstartout signal for one cycle. the fstartout signal overlaps the ?rst message bit of a reed-solomon code word. in the serial output mode, the L64724 chronologically orders the data. the msb is the oldest output and the lsb is the newest output. note that due to the use of a constant sampling frequency and the internal demodulator architecture, the output data stream in this mode contains gaps (when dvalidout is low.) the distribution and position in time of the gaps are governed mainly by the ratio of sampling frequency and symbol rate chosen. gaps can occur at any time in the output data stream. gap pclk fstartout co[0] dvalidout erroroutn n = code word length message bit 0 bit 1 bit 2 check bytes message L64724tm_300.book page 17 friday, april 14, 2000 2:17 pm
4-18 channel interfaces and data control L64724tm_300.book page 18 friday, april 14, 2000 2:17 pm
L64724 satellite receiver 5-1 chapter 5 demodulator module functional description this chapter describes the function of the L64724 bpsk/qpsk demodulator module and contains the following sections: section 5.1, overview section 5.2, analog to digital conversion section 5.3, dc offset compensation and coupling to adc output section 5.4, decimation filters section 5.5, matched filter section 5.6, timing clock recovery section 5.7, carrier recovery loop section 5.8, automatic gain control (agc) section 5.9, output control section 5.10, external controls L64724tm_300.book page 1 friday, april 14, 2000 2:17 pm
5-2 demodulator module functional description 5.1 overview the demodulator module connects to the satellite receiver circuitry in the set-top box to recover the modulated mpeg-2 transport stream. figure 5.1 shows the connections between the bpsk/qpsk demodulator and its associated circuitry. figure 5.1 demodulator module and associated circuitry 5.2 analog to digital conversion the L64724 incorporates two adcs at the front end to receive the incoming analog i and q data streams. the sampling clock to the adc is generated by an on-chip pll module. an externally applied signal on the clk pin drives the pll. for a detailed description of the pll, see chapter 4, "channel interfaces and data control." 2/t 1/t outputs to fec decoding pipeline matched filter section 5.5 output control section 5.9 timing loop section 5.6 carrier loop section 5.7 agc control section 5.8 L64724 demodulator tuner front end dual adc i/q down conv. gain control ampli?er agc loop filter pwrp interpolator / decimation section 5.4 external crystal oscillator L64724tm_300.book page 2 friday, april 14, 2000 2:17 pm
dc offset compensation and coupling to adc output 5-3 the internal adc produces six-bit samples that digitize the analog data streams into 64 discrete values, as shown in figure 5.2 . figure 5.2 input quantization 5.3 dc offset compensation and coupling to adc output the L64724 provides for an internal suppression of dc offsets on the i and q channels. the suppression feature is particularly useful when using an integrated front end that does not provide dc offset compensation pins and that introduces small offsets. dc offset compensation is controlled with the dc_offset_on_off[1:0] bits (see group 4, apr 23). the dc offset compensation can be accomplished with or without noise feedback, whichever best optimizes ber. noise feedback essentially shapes the quantization error spectrum. back end dc offset compensation (after the matched ?lter) is also provided and can be used if necessary. to enable this function, set the int_dc bit to 1 (group 4, apr 25). 1 - 1 - 2 adc input adc output 2 3 - 3 L64724tm_300.book page 3 friday, april 14, 2000 2:17 pm
5-4 demodulator module functional description 5.4 decimation filters the L64724 implements decimation ?lters on each i and q branch. the following decimation ratios can be selected through the df_ratio parameter (group 4, apr 19): 1, 1/2, 1/4, 1/8 and 1/16. these two ?lters enable the adc to operate at an oversampling ratio of n > 2. the ?lters operate at the adc sampling rate and generate down-sampled i and q streams from the sampled i and q inputs. the decimation and the sampling rate are con?gured to provide the highest possible number of samples per symbol with the tightest decimation ?lter available. the procedure is outlined in table 5.1 and the results are shown in table 5.2 . table 5.1 decimation procedure rs threshold (ms/s 1 ) 1. megasymbols per second (ms/s) df_ratio df_select df_gain group 4, register 19 setting fs (mhz) binary hex 45 to 44.5 1 0 1 10000100 0x84 91.5 (n = 1, s = 61, t = 10, m=3 44.5 to 30 1 0 1 10000100 0x84 see footnote 2 2. for rs <= 44.5 ms/s, calculate the sampling rate as follows: from the set of valid sampling frequency values, (30, 35, 40 ..., 85, 90), select the lower, closest value to 4 * df_ratio * rs/(1 + alpha), where alpha is the corner margin (1%). 30 to 15 1 1 1 00000100 0x04 see footnote 15 to 7.5 2 2 2 00101000 0x28 see footnote 7.5 to 3.75 4 3 4 01010001 0x51 see footnote 3.75 to 1 8 4 8 01111010 0x7a see footnote L64724tm_300.book page 4 friday, april 14, 2000 2:17 pm
decimation filters 5-5 table 5.2 decimation results rb (ms/s) sampling frequency (mhz) df_ratio samples per symbol df_filter df_gain 45 91.5 1 2.033 0 1 44.5 90 1 2.022 0 1 44 90 1 2.045 0 1 43 90 1 2.093 0 1 42 90 1 2.143 0 1 41 90 1 2.195 0 1 40 90 1 2.250 0 1 39 90 1 2.308 0 1 38 90 1 2.368 0 1 37 90 1 2.432 0 1 36 90 1 2.500 0 1 35 90 1 2.571 0 1 34 90 1 2.647 0 1 33 90 1 2.727 0 1 32 90 1 2.813 0 1 31 90 1 2.903 0 1 30 90 1 3 000 1 1 29 90 1 3.103 1 1 28 90 1 3.214 1 1 27 90 1 3.333 1 1 26 90 1 3.462 1 1 25 90 1 3.600 1 1 24 90 1 3.750 1 1 23 90 1 3.913 1 1 22.7250 85 1 3.740 1 1 21.4625 80 1 3.727 1 1 20.2000 75 1 3.713 1 1 18.9375 70 1 3.696 1 1 17.6750 65 1 3.678 1 1 16.4125 60 1 3.656 1 1 15.1500 55 1 3.630 1 1 (sheet 1 of 3) L64724tm_300.book page 5 friday, april 14, 2000 2:17 pm
5-6 demodulator module functional description 15 90 2 6.000 2 2 14 90 2 6.429 2 2 13 90 2 6.923 2 2 12 90 2 7.500 2 2 11.3625 85 2 7.481 2 2 10.7313 80 2 7.455 2 2 10.1000 75 2 7.426 2 2 9.4688 70 2 7.393 2 2 8.8375 65 2 7.355 2 2 8.2063 60 2 7.312 2 2 7.5750 55 2 7.261 2 2 7.5 90 4 12.000 3 4 7 90 4 12.857 3 4 6 90 4 15.000 3 4 5.6813 85 4 14.961 3 4 5.3656 80 4 14.910 3 4 5.0500 75 4 14.851 3 4 4.7344 70 4 14.785 3 4 4.4188 65 4 14.710 3 4 4.1031 60 4 14.623 3 4 3.7875 55 4 14.521 3 4 3.75 90 8 24.000 4 8 3 90 8 30.000 4 8 2.8406 85 8 29.923 4 8 2.6828 80 8 29.819 4 8 2.5250 75 8 29.703 4 8 2.3672 70 8 29.571 4 8 2.2094 65 8 29.420 4 8 2.0516 60 8 29.246 4 8 1.8938 55 8 29.043 4 8 table 5.2 decimation results (cont.) rb (ms/s) sampling frequency (mhz) df_ratio samples per symbol df_filter df_gain (sheet 2 of 3) L64724tm_300.book page 6 friday, april 14, 2000 2:17 pm
matched filter 5-7 5.5 matched filter the L64724 implements a matched ?lter with selectable roll-off factor on the i and q branches according to the dvb standard and dss speci?cations, respectively (square root raised cosine shape with roll-off b = 0.35 or 0.20). the roll-off factor is selected through the con?guration bit mf_20_35 (group 4, apr 20, bit 0). the ?lter operates at a constant input rate of 2/t. the roll-off factor is con?gured as shown in table 5.3 . 1.7359 50 8 28.803 4 8 1.5781 45 8 28.515 4 8 1.4203 40 8 28.163 4 8 1.2625 35 8 27.723 4 8 1.1047 30 8 27.157 4 8 1 30 8 30.000 4 8 table 5.2 decimation results (cont.) rb (ms/s) sampling frequency (mhz) df_ratio samples per symbol df_filter df_gain (sheet 3 of 3) table 5.3 roll-off factor mf_20_35 roll-off factor 0 0.20 (dss) 1 0.35 (dvb) L64724tm_300.book page 7 friday, april 14, 2000 2:17 pm
5-8 demodulator module functional description 5.6 timing clock recovery figure 5.3 illustrates the timing clock recovery loop. the L64724 clock synchronizer is implemented as an all-digital on-chip module requiring no external circuitry. the clock synchronizer generates the loop control signals for an internal nco and interpolator from the L64724 decimation filter output samples. the main elements in the timing recovery loop are the interpolators for the i and q components and the timing error detector. figure 5.3 clock recovery loop decimation timing loop filter filter matched filter/interpolator error detector interpolator resample adc i and q input samples control clk_mu_sel clk_bias register clk_lambda_sel register clk_alpha_sel mf_20_35 bit df_ratio register df_gain register df_select register timing lock detector clk_lc_thsl clk_lcf register bit register sweep generator clk_sw clk_swr bit register clk_uswl clk_lwsl register 30 4 4 8 3 3 2 16 16 16 register bit L64724tm_300.book page 8 friday, april 14, 2000 2:17 pm
timing clock recovery 5-9 5.6.1 clock acquisition and tracking modes the clock recovery loop operates in two modes: clock acquisition tracking in both modes, the clock recovery loop takes its input from the timing error detector (ted). the internal digital loop ?lter determines the loop characteristics using parameters clk_mu_sel, clk_lambda_sel, and clk_bias as well as the gains of the timing error detector and nco modules. the clk_mu_sel and clk_lambda_sel parameters are computed according to equation 5.1 , equation 5.2 , and equation 5.3 . equation 5.1 timing loop phase detector gain equation 5.2 symbol time equation 5.3 oversampling ratio fs is the sampling frequency, fb is the baud rate, and df_ratio is the decimation ?lter downsampling ratio, which can be 1, 2, 4, 8, or 16. based on the intermediate values t a and t b , given in equation 5.4 and equation 5.5 , the values for clk_mu_sel and clk_lambda_sel are computed in equation 5.6 and equation 5.7 . the damping factor ( z) is normally 1.0. the natural frequency ( w n ) of the loop is in radians/sec. equation 5.4 k dtim 0.0388 = t 1 fb ------- = l tim fs fb ------- 1 df_ratio ----------------------------- ? ?? = t a w n 2 t 2 k dtim l tim ------------------------- - = L64724tm_300.book page 9 friday, april 14, 2000 2:17 pm
5-10 demodulator module functional description equation 5.5 equation 5.6 clk_mu_sel equation 5.7 clk_lambda_sel during timing acquisition, the internal sweep mechanism can be used. to vary the sweep rate, change the value in the clk_swr register (group 4, apr 43 and 44). to start the sweep generator, set the clk_sw bit (group 4, apr 53) to 1. equation 5.8 gives the suggested value for the timing loop bandwidth. equation 5.8 the parameter timing_bw refers to the natural frequency w n .rsisthe symbol rate (rb = 1/tb). substitute the value of w n from equation 5.8 into the above equations for t a and t b . 5.6.1.1 timing loop sweep limits the clk_uswl (group 4, apr 45 and 46) and car_lswl[15:0] (group 4, apr 47 and 48) registers set the upper and lower timing loop sweep limits, respectively. figure 5.4 shows the timing loop sweep operation. t b 2 zw n t b k dtim l tim ------------------------- - = clk_mu_sel l og 2 t a 2 28 () = clk_lambda_sel l og 2 t b 2 16 () = timing _bw w n () 2 p rb msps [] 10 ----------------------------- = krad/s [] L64724tm_300.book page 10 friday, april 14, 2000 2:17 pm
timing clock recovery 5-11 figure 5.4 timing loop sweep operation 5.6.1.2 timing loop sweep equations and timing loop bias the equations for the sweep rate and sweep limit are given below in equation 5.9 and equation 5.10 . sweeprate indicates the desired sweep rate in hz/sec and df_ratio is the decimation ?lter down sampling ratio, which can be 1, 2, 4, 8 or 16. t is the symbol time and fs is the sampling (a/d) frequency. equation 5.9 clk_swr choose clk_uswl or clk_lswl as given in equation 5.10 . sweeplimit indicates the upper desired sweep limit in hz for clk_uswl and it indicates the lower limit for clk_lswl. equation 5.10 clk_uswl note that x stands for either u or l. also, you must set the appropriate sweeplimit. choose clk_bias according to equation 5.11 . equation 5.11 clk_bias where fs = sampling frequency, and fb = baud rate. frequency time lower sweep limit upper sweep limit sweep start point clk_swr 2 42 sweeprate tb fs 1 df_ratio ------------------------ - ----------------------------------------------------------- - = clk_xswl 2 24 sweeplimit fs 1 df_ratio ------------------------ - ---------------------------------------------- = clk_bias 2 27 fs fb ------- 1 df_ratio ----------------------------- ? ?? = L64724tm_300.book page 11 friday, april 14, 2000 2:17 pm
5-12 demodulator module functional description 5.7 carrier recovery loop figure 5.5 illustrates the L64724 carrier recovery loop. this circuit consists of the following main functional elements: phase error detector digital loop ?lter phase lock detector frequency sweep generator frequency lock detector figure 5.5 carrier recovery loop output dual adc interpolator/ decimation filter matched filter phase error detector digital loop filter car_ped_sel bit sweep generator car_sw car_swr bit register 4 car_mu_sel register 4 car_lambda_sel register car_uswl car_lwsl registers phase lock detector car_lc bit matched filtered i and q samples car_lc_thsl 8 register car_open bit car_lf_init register 24 frequency 16 16 16 L64724tm_300.book page 12 friday, april 14, 2000 2:17 pm
carrier recovery loop 5-13 because the outputs of off-the-shelf tuners for dvb satellite receivers have a large frequency uncertainty (a common order of magnitude is 5 mhz), the L64724 carrier synchronizer includes a frequency sweep generator for signal acquisition. the L64724 implements the entire carrier recovery loop digitally. 5.7.1 carrier acquisition during carrier acquisition, the internal frequency sweep generator searches for the correct frequency. to vary the sweep rate, change the value in the car_swr register (group 4, apr 32, 33). to start the sweep generator, set the car_sw bit (group 4, apr 41) to 1. 5.7.1.1 frequency sweep limits the car_uswl (group 4, apr 34, 35) and car_lswl (group 4, apr 36, 37) registers set the upper and lower limits, respectively, of the frequency sweep. 5.7.1.2 frequency sweep in the case shown in figure 5.6 , both the car_uswl (group 4, apr 34, 35) and car_lswl (group 4, apr 36, 37) registers must be set. the state of the car_swp_swap (group 4, apr 41) bit controls the sweep direction. even though the carrier synchronizer controls the frequency sweep rate based on the value in the car_swr register (group 4, apr 32, 33), the microcontroller can monitor the sweep direction itself. figure 5.6 frequency sweeping frequency lower sweep limit upper sweep limit sweep start point time L64724tm_300.book page 13 friday, april 14, 2000 2:17 pm
5-14 demodulator module functional description if the car_auto_swp (group 4, apr 41) bit is used, the sweep waveform is similar to that shown in figure 5.6 , where the sweep direction changes once the upper or lower limit is reached. 5.7.1.3 frequency sweep rate the carrier synchronizer determines the frequency sweep rate based on the value in the car_swr register. set the value in the 16-bit car_swr register based on equation 5.12 . equation 5.12 5.7.1.4 car_swr the suggested value for car_swr can be derived by calculating the value for sweep_rate as shown in equation 5.14 and substituting it in equation 5.13 . equation 5.13 equation 5.14 rs is the symbol rate and m and n are as shown in the following table. to provide reliable acquisition at any signal-to-noise ratio, the microcontroller uses two sweep rates. the fast rate pulls the loop out of sweep_rate car_swr B fs t 2 33 ----------------------------------------- ? ? ?? = rs (ms/s) m n 45 to 15 32 8 15 to 7.5 8 2 7.5 to 3.75 8 1 3.75 to 2 8 1 2to1 4 1 car_swr 2 34 sweeprate t b fs ---------------------------------------------------------- = slow_sweep_rate[mhz/s] n x rs ms/s [] = fast_sweep_rate[mhz/s] m x rs ms/s [] = L64724tm_300.book page 14 friday, april 14, 2000 2:17 pm
carrier recovery loop 5-15 false locks. the parameters in the above table might have to be adjusted at very low rates (< 2 ms/s) for optimal performance, depending on the tuner. choose car_lswl and car_uswl as given below. sweeplimit indicates the upper desired sweep limit in hz for car_uswl and it indicates the lower limit for car_lswl. equation 5.15 in order to initialize the carrier frequency deviation to any desired value, use the car_lf_init register from group 3. in equation 5.16 , freqdeviation is the desired frequency deviation in hz and fs is the sampling (a/d) frequency. calculate car_lf_init as shown in equation 5.16 . equation 5.16 the carrier frequency deviation can be read back from car_ncof in group 3, apr 7, 8, and 9. equation 5.17 is the equation for frequency deviation. equation 5.17 5.7.1.5 phase lock detection when the carrier frequency is close enough to the frequency of the incoming wave, the carrier signal lies in the pull-in range of the phase- locked-loop. when the loop is phase locked, the phase lock detector sets the car_lc bit (group 3, apr 11) to 1. to stop the sweep, the microprocessor must then set the car_sw bit (group 4, apr 41) to 0. car_xswl 2 16 sweeplimit fs ---------------------------------------------- = car_lf _init 2 24 freqdeviation fs ----------------------------------------------------- = frequencydeviation (hz) fs car_ncof 2 24 ---------------------------------------------- = L64724tm_300.book page 15 friday, april 14, 2000 2:17 pm
5-16 demodulator module functional description the phase lock detector uses a internal threshold and an estimation period, which are programmable using the car_lc_thsl register (group 4, apr 29). the fp_lock_len bit (group 4, apr 54) selects between a long and short estimation period. for operation at low e b /n o (less than 10 db), the long period should be selected (fp_lock_len = 0). a typical value of car_lc_thsl is then 31. for operation at higher e b /n o (10 db or higher), the short period can be selected, which provides for a faster lock detection. in this case, a typical value for car_lc_thsl is 72. 5.7.1.6 false locks the microcontroller must take particular care to handle a false lock condition correctly. a false lock occurs when phase lock has been detected but the correct central frequency has not yet been reached. this situation occurs in qpsk for frequency offsets that are multiples of 1/4 t, where t is the qpsk symbol duration, and also at other offsets dictated by the discrete nature of the carrier recovery loop. offsets that are not multiples of 1/4 t are hard to predict. 5.7.2 carrier phase tracking the following subsections give a detailed description of the phase error estimator and the carrier recovery loop characteristics. 5.7.2.1 phase error estimator in qpsk mode (the qb bit in group 4, apr 2 is 0), the phase error detector implements two error estimators: nondata aided maximum likelihood (ndaml) decision directed maximum likelihood (ddml) the microcontroller selects the estimator using the car_ped_sel bit (group 4, apr 41). when the car_ped_sel is 0, the ddml estimator is used. when the bit is 1, the ndaml estimator is used. in bpsk mode (the qb bit is 1 in group 4, apr 2), the phase error detector implements a single ddml estimator. L64724tm_300.book page 16 friday, april 14, 2000 2:17 pm
carrier recovery loop 5-17 the phase detector uses two gain values depending on the signal to noise ratio. the snr is internally estimated and compared to the snr_ths[7:0] 8-bit threshold (group 4, apr 27). the plot in figure 5.7 shows the relationship between the snr_ths[7:0] parameter and the actual e s /n o (symbol energy to noise power density) seen in-circuit. a value of 100 is recommended for snr_ths[7:0]. the value of 100 corresponds to an actual e s /n o of 11 db. the result of the comparison of the estimated snr to the threshold is stored in the demod_snr bit (group 3, apr 6, bit 7). a 12-bit value for this snr estimate is available from snr[11:0] in group 3, apr 22 and 23. figure 5.7 snr threshold vs. e s /n o 5.7.2.2 loop characteristics to set the parameters of the carrier recovery loop (natural frequency and damping factor), the user must select the values the microprocessor writes into the car_mu_sel and car_lambda_sel (group 4, apr 28) registers. figure 5.8 carrier loop filter parameters the values of car_mu_sel and car_lambda_sel are computed according to equation 5.18 , equation 5.19 , and equation 5.20 . e s /n o [db] L64724tm_300.book page 17 friday, april 14, 2000 2:17 pm
5-18 demodulator module functional description equation 5.18 carrier loop phase detector gain k digital is a function of snr (see table 5.4 on page 5-19 ). equation 5.19 symbol time equation 5.20 oversampling ratio fs is the sampling frequency and fb is the baud rate based on the intermediate values t a and t b , which are calculated in equation 5.21 and equation 5.22 , car_mu_sel and car_lambda_sel are computed as shown in equation 5.23 and equation 5.24 . the damping factor ( z) is normally 1.0. the natural frequency ( w n ) of the loop is in radians/sec. equation 5.21 equation 5.22 equation 5.23 equation 5.24 k dcar (or k digital ) is the carrier loop phase detector gain. it is a function of snr as well as the mode (ddml or ndaml). table 5.4 presents the gains of the two phase detectors as a function of snr. k dcar k digital 0.78 32 ------------------------------- = t b 1 fb ------- = l car fs fb ------- = t a w n 2 t b () 2 k dcar l car -------------------------- - = t b 2 zw n t b k dcar l car -------------------------- - = car_mu_sel l og 2 t a 2 25 () = car_lambda_sel l og 2 t b 2 16 () = L64724tm_300.book page 18 friday, april 14, 2000 2:17 pm
carrier recovery loop 5-19 table 5.4 ped gain for carrier loop snr (db) k digital ddml k digital ndaml 1 4.26 4.39 2 5.91 6.19 3 8.36 8.16 4 11.65 10.66 5 14.76 13.59 6 16.77 16.78 7 19.25 20.18 8 20.74 23.39 9 23.00 26.67 10 24.39 29.58 12 25.39 34.38 14 25.61 37.82 16 25.89 40.26 18 26.02 41.75 20 26.10 42.71 25 26.10 43.34 L64724tm_300.book page 19 friday, april 14, 2000 2:17 pm
5-20 demodulator module functional description the suggested value for w n is shown in equation 5.25 . equation 5.25 suggested values for w n the value of w n from equation 5.25 can be substituted in the carrier loop equations, equation 5.21 and equation 5.22 ,for t a and t b . here carrier_bw refers to the natural frequency w n . rs (1/t) is the symbol rate. 5.8 automatic gain control (agc) this section describes the L64724 automatic gain control (agc) function. 5.8.1 adc range and power reference when the pwr_ref register (group 4, apr 24) is set to the recommended value of 84, the agc sets the ratio of the signal range to the adc range to 1:1.7 (see figure 5.9 .) figure 5.9 eye pattern and adc range carrier_bw w n () 2 p rb ms / s [] = 2 * r = 3.4 1.7 1.0 0.0 -1.0 -1.7 t / symbol period voltage 0.0 0.5 1.0 2s = input signal range L64724tm_300.book page 20 friday, april 14, 2000 2:17 pm
automatic gain control (agc) 5-21 assuming that the signal power at the input of the adc is normalized to 1v 2 , the range of the signal (2s) is 2 v (the noise-free level of the i and q signals). the value of pwr_ref is computed from equation 5.26 . equation 5.26 e s is the signal energy, n i is the interference power, p s is the signal power of the desired channel, w s is the bandwidth of the saw, and r is the baud rate. 5.8.2 power control loop the L64724 measures the signal power at the output of the matched ?lter and compares the measured value to an expected value that the microcontroller has written into the pwr_ref register. the microcontroller can adjust the power loop bandwidth using the pwr_bw[1:0] bits (group 4, apr 25). the loop bandwidth is proportional to the value of pwr_bw[1:0] and proportional to the symbol rate. set the pwr_bw bits according to table 5.5 . the power control signal drives the sigma-delta modulated output pwrp. use the pwrp output to drive an external passive rc ?lter that feeds the gain control stage (see figure 5.10 .) pwr _ ref min 84 84 1 e s n o ------- ? ?? 1 C + df _gain 2 1 n i p s ------ - ? ?? e s n o ------- ? ?? 1 C w s r -------- - ? ?? ++ -------------------------------------------------------------------- , ?t ?? ?? y ?? ?? = table 5.5 pwr_bw as a function of symbol rate pwr_bw[1:0] symbol rate (mhz) 0b00 20C45 0b01 10C20 0b10 5C10 0b11 2C5 L64724tm_300.book page 21 friday, april 14, 2000 2:17 pm
5-22 demodulator module functional description figure 5.10 agc loop control the r and c values for the passive low-pass ?lter should meet the requirements of equation 5.27 . equation 5.27 5.8.3 power level the L64724 stores the agc loop control voltage in the pwr_lvl[7:0] register (group 3, apr 10), where the microcontroller can monitor it. the relationship between the loop voltage v agc and the pwr_lvl register is shown in equation 5.28 . equation 5.28 the pwrp pin uses an open drain buffer that allows you to apply an external v ref voltage of 5 v even if the L64724 is powered at 3.3 v. 5.9 output control because the output of the matched ?lter is quantized to four bits for the subsequent viterbi decoder, the L64724 output control properly adjusts the level of the output signals. the microcontroller can adjust the level of the demodulated demi and demq output signals using the scale register (group 4, apr 26). the scale register multiplies the results of the matched ?lter before it is truncated to the 4-bit outputs. v agc r agc ~ 2.7 k c agc ~ 22 nf n p pwr r ~ 470 w 5 v r agc c agc 64 m s @ v agc pwr_lvl 256 --------------------------- - v ref = L64724tm_300.book page 22 friday, april 14, 2000 2:17 pm
external controls 5-23 when the pwr_ref register (group 4, apr 24) is set to its recommended value of 84, the value of the scale[7:0] bits should be set to 158. 5.9.1 eye pattern and soft decision thresholds the useful part of the matched ?lter output signal is clipped for a larger value of scale. because the power control loop automatically reduces the eye amplitude for increasing noise, the demi and demq signals include additional headroom for resolving noise. equation 5.29 and equation 5.30 relate scale and pwr_ref. equation 5.29 scale and pwr_ref relationship for qpsk systems equation 5.30 scale and pwr_ref relationship for bpsk systems 5.10 external controls external controls have been added in order to simplify the design of the analog front end, to reduce the amount of external circuitry, and to make the board layout as simple as possible. five external control bits are available on the L64724. four of these bits (xctr_out[3:0]) are output signals, and one (xctr_in) is an input signal. the controls can be used to setup or to read parameters from other components on the board (such as the rf front end and the tuner) using only the L64724 microprocessor interface. the four output controls use pins xctr_out[3:0], which are programmed by setting their respective bits in the xctr[3:0] register scale 2047 1 e s n o ------- ? ?? 1 C + 2 pwr_ref -------------------------------------------------- = scale 2047 1 e s n o ------- ? ?? 1 C + 2 pwr_ref -------------------------------------------------- = L64724tm_300.book page 23 friday, april 14, 2000 2:17 pm
5-24 demodulator module functional description (group 4, apr 55). the xctr[i] register drives the xctr_out[i] pin that is, programming the xctr[i] register to 0 deasserts pin xctr_out[i] to a zero-volt level, and programming the xctr[i] register to 1 asserts pin xctr_out[i] to a 3.3 volt level. the input control is sensed on the xctr_in pin. the logic level applied to this pin is read using the xctr_in bit (group 3, apr 6). L64724tm_300.book page 24 friday, april 14, 2000 2:17 pm
L64724 satellite receiver 6-1 chapter 6 decoding pipeline synchronization this chapter describes the con?gurable synchronization circuit that aligns the decoding pipeline outputs to the overall frame structure of the L64724. the decoding pipeline consists of the viterbi decoder, deinterleaver, reed-solomon (rs) decoder, and the descrambler. this chapter contains the following sections: section 6.1, synchronization scheme section 6.2, viterbi decoder synchronization section 6.3, reed-solomon deinterleaver synchronization section 6.4, descrambler synchronization 6.1 synchronization sc heme the L64724 fec synchronization scheme is accomplished in three stages: the ?rst synchronization stage uses output statistics from the viterbi decoder module. the second stage identi?es a synchronization word. the third stage identi?es an inverted synchronization word. a global control module generates the control signals for the viterbi, descrambler, deinterleaver, and rs decoder modules. the global control module handles the appropriate sequencing of the synchronization signals for determining in- and out-of-synchronization. the input to the fec portion of the L64724 is two symbols generated by the demodulator portion. the maximum information rate is 90 mbits/s. figure 6.1 shows the organization of the synchronization module. L64724tm_300.book page 1 friday, april 14, 2000 2:17 pm
6-2 decoding pipeline synchronization figure 6.1 synchronization module 6.2 viterbi decoder synchronization this section describes the ?rst stage of the synchronization module, which performs viterbi decoder synchronization. in the ?rst stage, the decoder observes the valid data symbols and bit errors in the decoded data stream to determine the in- or out-of- synchronization condition. the viterbi max data bit count registers (vmdc1 in group 4, apr 4, and vmdc2 in group 4, apr 5C7) set the number of valid data bits at the output of the viterbi decoder over which the decoder counts channel symbol errors. during that interval, whenever the bit error count is above the value speci?ed in the viterbi max data bit error count register (group 4, apr 8C13,) the synchronization logic ?ags an out-of-synchronization condition. figure 6.2 shows the viterbi decoder synchronization. viterbi in sync/ viterbi decoder de- rs decoder viterbi di rs global control data data data data con?guration parameters out of sync bit error monitor rs/di data in sync/ out of sync inter- leaver data descr. descrambler control signals control control in sync/ out of sync data descrambler sync. module sync. module sync. module data control third stage second stage first stage viterbi decoder synchronization reed-solomon deinterleaver synchronization descrambler synchronization L64724tm_300.book page 2 friday, april 14, 2000 2:17 pm
viterbi decoder synchronization 6-3 figure 6.2 viterbi decoder synchronization the decoder then proceeds to adjust either the phase in the phase rotation module or the data stream alignment in the depuncturing logic. the 180 degree rotation is removed in the reed-solomon decoder synchronization stage (see section 6.3, reed-solomon deinterleaver synchronization, page 6-8 .) figure 6.3 outlines the operations performed during phase rotation. i-channel q-channel phase rotation depuncturing logic bit error count decoded data viterbi decoder decoder data bit count max bit error count max data bit count decision logic rotate phase sync in-sync/out-of-sync (vmdc1 & 2) (vmbec) group 4, apr 4C13 registers L64724tm_300.book page 3 friday, april 14, 2000 2:17 pm
6-4 decoding pipeline synchronization figure 6.3 phase rotation for synchronization this ?rst synchronization stage does not inspect the data stream for speci?c synchronization patterns, nor does it remove any portions of the data stream. once the viterbi decoder module has reached synchronization, the deinterleaver and reed-solomon blocks in the data pipeline each require their own synchronization procedures. the data bit count and bit error count threshold values are vmdc1 (group 4, apr 4) and vmbec (group 4, apr 8C13.) to assist you in the proper selection of the ratio (vmbec/vmdc1) of the threshold values, figure 6.4 through figure 6.9 show the plots of the channel symbol error rate vs. snr for all the code rates that the L64724 supports. the upper curve in each graph represents the out-of-synchronization condition, and the lower curve represents the in-synchronization condition. i input q input i output = q input q output = i input phase rotation i input q input i output = i input q output = q input L64724tm_300.book page 4 friday, april 14, 2000 2:17 pm
viterbi decoder synchronization 6-5 figure 6.4 channel symbol error rate vs. snr for rate = 1/2 code figure 6.5 channel symbol error rate vs. snr for rate = 2/3 code snr = e s /sigma^2 [db] snr = e s /sigma^2 [db] L64724tm_300.book page 5 friday, april 14, 2000 2:17 pm
6-6 decoding pipeline synchronization figure 6.6 channel symbol error rate vs. snr for rate = 3/4 code figure 6.7 channel symbol error rate vs. snr for rate = 5/6 code snr = e s /sigma^2 [db] snr = e s /sigma^2 [db] L64724tm_300.book page 6 friday, april 14, 2000 2:17 pm
viterbi decoder synchronization 6-7 figure 6.8 channel symbol error rate vs. snr for rate = 6/7 code figure 6.9 channel symbol error rate vs. snr for rate = 7/8 code you must select a value for the ratio vmbec/vmdc1 that is between the in-synchronization and the out-of-synchronization curves. for example, for a rate equal to 1/2 code, a value of 0.24 for vmbec/vmdc1 establishes a valid decision threshold over the entire e b /n o range shown. snr = e s /sigma^2 [db] snr = e s /sigma^2 [db] L64724tm_300.book page 7 friday, april 14, 2000 2:17 pm
6-8 decoding pipeline synchronization equation 6.1 shows the computation of channel symbol error rate as a function of vmbec and vmdc1. equation 6.1 6.3 reed-solomon deinterleaver synchronization this section describes the second synchronization stage, which performs reed-solomon deinterleaver synchronization. in the second synchronization stage, the decoder searches the data stream for a predefined sync word to determine the in-sync or out-of-sync condition. figure 6.10 illustrates the reed-solomon deinterleaver synchronization module, which is designed to allow synchronization for dvb (digital video broadcast) as well as for dss (digital satellite systems) compliant systems. figure 6.10 reed-solomon, deinterleaver synchronization channel symbol error rate 128 vmbec 32 + 256 vmdc 1 ---------------------------------------------- = data stream decision logic con?guration parameters sync strobes bit stream monitor m, n, l, k mc, lsc sync word reed-solomon decoder module deinterleaver module L64724tm_300.book page 8 friday, april 14, 2000 2:17 pm
reed-solomon deinterleaver synchronization 6-9 figure 6.11 shows an example state diagram that outlines how the decoder determines synchronization, tracking, and loss of synchronization in the reed-solomon synchronization stage. figure 6.11 synchronization, tracking, and loss of sync for three missed sync words the parameters in figure 6.11 are de?ned as follows: acquisition phase pa tracking phase loss of sync pa: state transition, sync word detected qa: state transition, sync word misdetected pa pa pt: state transition, sync word detected qt: state transition, sync word not detected pt pt pt qt qt qt qa qa qa synchronization state (sst = 0b01) msc = 1 msc = 2 mc = 1 mc = 2 mc = 0 msc = 0 mc = 3 reacquire sync synchronization state: (ssa = 0b00) parameter description mc match counternumber of sync word matches found so far during the acquisition phase msc mismatch counternumber of sync word mismatches found so far during the tracking phase pa, pt pa and pt are functions of l, which is de?ned as the maximum number of mismatching bits allowed to declare a match when comparing m bits in the data stream to the reference sync word during tracking phase (l = 0, 1, or 2). L64724tm_300.book page 9 friday, april 14, 2000 2:17 pm
6-10 decoding pipeline synchronization you can con?gure some of the parameters in the state diagram for the acquisition and tracking phase. for example, you can set the ssa parameter (group 4, apr 16) to allow for three, four, ?ve, or six sync words before the decoder declares itself to be in synchronization. you can also set the sst parameter (group 4, apr 16) to allow for two, three, four, or ?ve misdetected sync words before the decoder declares a loss of synchronization. figure 6.12 and figure 6.13 show the minimum and maximum number of states that you can select for acquisition and tracking modes. figure 6.12 minimum and maximum number of states in the acquisition phase qa pa mc = 3 from tracking phase acquisition phase (maximum number of states) pa pa qa qa qa mc = 1 mc = 2 mc = 0 synchronization state (ssa = 0b11) qa pa mc = 5 pt msc = 0 mc = 6 from tracking phase acquisition phase (minimum number of states) pa pa qa qa qa mc = 1 mc = 2 mc = 0 synchronization state: (ssa = 0b00) pt msc = 0 mc = 3 pa pa qa pa mc = 4 L64724tm_300.book page 10 friday, april 14, 2000 2:17 pm
reed-solomon deinterleaver synchronization 6-11 figure 6.13 minimum and maximum number of states in the tracking phase the data structure for dss systems is shown in figure 6.14 . a dss packet consists of 146 bytes, including 130 data bytes and 16 redundancy bytes. a synchronization byte precedes every reed- solomon block, but is added after the reed-solomon encoding and interleaving operations have been performed. the sync byte is removed in the bit stream monitor and is not supplied to the deinterleaver and reed-solomon decoder modules. from tracking phase (minimum number of states) loss pa pt pt qt qt synchronization state (sst = 0b00) msc = 1 msc = 0 acquisition phase of sync reacquire from tracking phase (maximum number of states) pa pt pt pt qt qt qt synchronization state (sst = 0b11) msc = 1 msc = 2 msc = 0 acquisition phase pt qt msc = 3 reacquire pt qt msc = 4 L64724tm_300.book page 11 friday, april 14, 2000 2:17 pm
6-12 decoding pipeline synchronization figure 6.14 dss packet an mpeg-2 rs(204,188) protected transport packet consists of 204 bytes, including 1 sync byte, 187 data bytes, and 16 redundancy bytes. figure 6.15 shows the data format of the mpeg-2 transport packet. figure 6.15 mpeg-2 transport packet in the dvb data structure, one out of every eight synchronization words in the data stream is mod 2 complemented. figure 6.16 shows the data format of the L64724 transport packet. figure 6.16 L64724 transport packet given a bit stream that consists of a sequence of the packets shown in figure 6.16 , the second synchronization stage searches for the prede?ned sync byte. in addition to providing the proper data alignment for the deinterleaver and reed-solomon decoder modules, the second synchronization stage (reed-solomon deinterleaver synchronization) resolves the 180-degree phase uncertainty that the upstream demodulator may have introduced. the ?rst (viterbi) synchronization stage is not able to detect a phase uncertainty error. 130 data bytes sync byte rs(146,130) 16 bytes 146 bytes 187 data bytes sync byte rs(204,188) 16 bytes 204 bytes sync byte 8 x 204 bytes inverted sync byte inverted sync byte 204 bytes L64724tm_300.book page 12 friday, april 14, 2000 2:17 pm
descrambler synchronization 6-13 6.4 descrambler synchronization this section describes the third-stage synchronization, which performs descrambler synchronization. figure 6.17 illustrates the descrambler synchronization process. the descrambler module is only active in dvb systems and is not used for dss systems. the L64724 restarts the descrambler every 8n byte times. the L64724 aligns this restart with the complemented synchronization word that is present in the data stream once every eight reed-solomon code words (once every 8 n bytes.) figure 6.17 descrambler synchronization for third-stage synchronization, the L64724 uses an approach very similar to that of the second synchronization stage during the acquisition phase to ensure proper data alignment. note that in this stage, any noninverted corrupted sync bytes found in the tracking phase are replaced with the original prede?ned noninverted sync byte. data stream decision logic con?guration parameters sync strobes bit stream monitor m, n, l, k mc, lsc sync word module descrambler data L64724tm_300.book page 13 friday, april 14, 2000 2:17 pm
6-14 decoding pipeline synchronization L64724tm_300.book page 14 friday, april 14, 2000 2:17 pm
L64724 satellite receiver 7-1 chapter 7 the fec decoder pipeline this chapter discusses the fec decoder pipeline. the decoder pipeline consists of four modules that are connected in a logical sequence. this chapter discusses the four modules in the pipeline in the following sections: section 7.1, viterbi decoder module section 7.2, deinterleaver module section 7.3, reed-solomon decoder section 7.4, descrambler module architecture and operation section 7.5, fec module software reset 7.1 viterbi decoder module the viterbi decoder contains the following major modules: a depuncture module for code rates other than 1/2 a 1/2 code rate viterbi decoder that computes the serial output data stream given two sets of soft decision data input streams a synchronization monitor to provide information on acquisition or loss of synchronization a bit error rate (ber) monitor the block diagram in figure 7.1 shows the viterbi decoder. L64724tm_300.book page 1 friday, april 14, 2000 2:17 pm
7-2 the fec decoder pipeline figure 7.1 viterbi decoder block diagram 7.1.1 features the viterbi decoder module has the following features: a viterbi decoder with a basic rate of 1/2 compliant with european digital video broadcast (dvb-s) depuncturing for code rates of 2/3, 3/4, 5/6, 6/7 and 7/8 compliant with dvb and dss channel coding speci?cations programmable viterbi code rates of 1/2, 2/3, 3/4, 5/6, 6/7, 7/8 auto code rate, phase inversion, synchronization for viterbi decoder with programmable threshold auto-rate acquisition over the dvb and dss code range rate detection over the dvb code range constraint length of 7 synchronization monitor decoded ber monitor maximal likelihood (ml) decoding algorithm 5.2 db coding gain for rate 1/2 (no erased input) code at ber of 10 -5 generating polynomial 171 (octal) and 133 (octal) (rate = 1/2) viterbi decoder decoded sync sync monitor symbol 0 symbol 1 modem format code rate control depuncture module bit error ber monitor rate imq status data L64724tm_300.book page 2 friday, april 14, 2000 2:17 pm
viterbi decoder module 7-3 7.1.2 punctured codes the L64724 supports not only the basic rate equal to 1/2 decoding operations, but also code rates equal to 2/3, 3/4, 5/6, 6/7 and 7/8. the code rate and underlying depuncture scheme chosen dictates the proper sequence of symbols on the dem_i and dem_q inputs. table 7.1 shows the puncture patterns for various code rates. figure 7.2 shows a block diagram of the puncturing and depuncturing process for a rate 1/2 encoder. for each data bit d n , the upstream encoder generates two corresponding encoded data symbols, i. n and q. n. by deleting or puncturing some of the encoded data symbols, the puncturing process allows a rate 1/2 encoder to generate codes of higher rates. the L64724s depuncturing module allows its rate 1/2 decoder to decode data transmitted at higher code rates. figure 7.3 illustrates the puncture patterns for different code rates. table 7.1 puncture patterns for various code rates code rate puncture pattern 1/2 dem_i: dem_q: 1 1 2/3 dem_i: dem_q: 10 11 3/4 dem_i: dem_q: 101 110 5/6 dem_i: dem_q: 10101 11010 6/7 dem_i: dem_q: 100101 111010 7/8 dem_i: dem_q: 1000101 1111010 L64724tm_300.book page 3 friday, april 14, 2000 2:17 pm
7-4 the fec decoder pipeline figure 7.2 puncturing and depuncturing block diagram the L64724 receives the encoded data symbols in qpsk or bpsk format on the ivin and qvin signals. the L64724 receives these symbols in the order shown on the right of L64724 input data in figure 7.2 . the depuncturing module handles the reordering and the insertion of erasures into the received symbol stream before the rate equal to 1/2 viterbi decoder module starts decoding. viterbi encoder L64724 rate = 1/2 depuncture module rate = 1/2 encoder puncture module comm. channel input data encoded data punctured data depunctured data d1 d2 d3 d4 d5 d6 d7 d8 input data encoded data i.1 i.2 i.3 i.4 i.5 i.6 i.7 i.8 q.1 q.2 q.3 q.4 q.5 q.6 q.7 q.8 fifo/ viterbi decoder decoded output data modulator demod. L64724tm_300.book page 4 friday, april 14, 2000 2:17 pm
viterbi decoder module 7-5 figure 7.3 puncture pattern for different code rates punctured data i.1 i.2 i.3 i.4 q.1 q.2 q.3 q.4 punctured symbol (deleted) i.1 q.1 viterbi input data (qpsk) rate 2/3 punctured data i.1 i.2 i.3 q.1 q.2 q.3 i.1 q.1 rate 3/4 q.2 i.3 q.2 i.3 q.3 q.4 i.1 i.3 q.1 q.3 q.2 q.4 i.1 i.3 q.1 q.2 viterbi input data (bpsk) viterbi input data (qpsk) viterbi input data (bpsk) i q i i q i L64724tm_300.book page 5 friday, april 14, 2000 2:17 pm
7-6 the fec decoder pipeline figure 7.3 puncture pattern for different code rates (cont.) punctured symbol (deleted) punctured data i.1 i.2 i.3 i.4 i.5 i.6 q.1 q.2 q.3 q.4 q.5 q.6 i.1 q.1 rate 7/8 i.7 q.7 q.2 q.3 q.4 i.5 q.6 i.7 i.1 q.3 q.1 q.2 L64724 input data (bpsk) L64724 input data (qpsk) i.5 q.4 i q i i.7 q.6 punctured data i.1 i.2 i.3 i.4 i.5 q.1 q.2 q.3 q.4 q.5 i.1 q.1 rate 5/6 q.2 i.3 q.4 i.5 i.1 i.3 q.1 q.2 viterbi input data (qpsk) viterbi input data (bpsk) i.5 q.4 i q i punctured data i.1 i.2 i.3 i.4 i.5 i.6 q.1 q.2 q.3 q.4 q.5 q.6 i.1 q1 rate 6/7 i.7 q.7 q.2 q.3 i.4 q.5 i.6 q.7 i.1 i.3 i.1 i.2 viterbi input data (bpsk) viterbi input data (qpsk) i.5 i.4 i q i i.7 i.6 i.8 i.9 i.10 i.11 q.8 q.9 q.10 q.11 i.12 q.12 i.7 q.8 i.9 q.10 i.11 q.12 L64724tm_300.book page 6 friday, april 14, 2000 2:17 pm
viterbi decoder module 7-7 7.1.3 viterbi ber monitor a performance monitor for the channel ber is built into the L64724. the monitor compares an appropriately delayed version of the incoming channel data stream to the re-encoded viterbi decoder output data stream to ?nd occurrences of bit errors. figure 7.4 is a block diagram of the viterbi bit error detection circuit. figure 7.4 block diagram of viterbi bit error detection circuit the decoder processes the bit error events further to produce a measure of the actual channel bit error rate. the register vmdc2 (group 4, apr 5C7) speci?es the number of channel bits (and therefore the time period), divided by four, over which the decoder counts the number of occurring channel bit errors. refer to section 3.6.6, viterbi max data bit count 2 (group 4: apr 5, 6, and 7), page 3-42 , for a description of vmdc2. the channel data error counter accumulates the errors internally and updates the viterbi bit error rate count (vberc, group 3, apr 4:5) once at the end of the period speci?ed by vmdc2. you can read the value of the vberc using the microcontroller interface. vberc contains the number of errors divided by four. in addition, the L64724 sets the vber ?ag in the system status register (group 2.) the vber ?ag indicates that the decoder has reached the period speci?ed by vmdc2. rate = 1/2 viterbi decoder core decoded data symbol 0 symbol 1 depuncture module comparator depunctured max data bit count (vmdc2) channel data error count bit error 24 16 count con?guration parameter data L64724tm_300.book page 7 friday, april 14, 2000 2:17 pm
7-8 the fec decoder pipeline the decoder asserts intn if the corresponding interrupt enable bit, vber_ie, is set in the system mode register (group 2.) refer to section 3.4, group 2: system mode and system status registers, page 3-9 , for details. the ber curves to assist in the proper selection of the ratio of the threshold values vmdc1 and vberc are shown in section 6.2, viterbi decoder synchronization, page 6-2 . 7.2 deinterleaver module figure 7.5 shows the interleaving/deinterleaving operation for the dvb mode. figure 7.5 interleaving/deinterleaving operation for dvb the interleaver is a device that rearranges the ordering of a sequence of symbols in a deterministic manner. a (b, n) periodic interleaver has the following characteristics: the minimum separation at the interleaver output is b symbols for any two symbols that are separated by less than n symbols at the interleaver input. if the channel inserts any burst of less than b errors, single errors occur at the deinterleaver output. this scheme is also known as a convolutional interleaver/deinterleaver. m 2m (b - 1)m m 2m (b - 1)m from encoder channel to decoder L64724tm_300.book page 8 friday, april 14, 2000 2:17 pm
deinterleaver module 7-9 the L64724 deinterleaver module performs periodic deinterleaving. the user must specify two parameters: b, the desired interleaving depth, and m, de?ned as . the L64724 deinterleaver for dvb features are as follows: convolutional deinterleaving maximum block length of 204 bytes deinterleaving depth of 12 figure 7.6 shows the interleaving/deinterleaving operation for the dss mode. figure 7.6 interleaving/deinterleaving operation for dss the L64724 uses a ramsey type ii periodic deinterleaver for dss deinterleaving. a (b, n) periodic deinterleaver has the following characteristics: m n b ---- = n2 0 1 k - 1 n2 k - 1 1 0 0 1 n1 - 1 (n1 - 1)(k - 1) n2(n1 - 1) tap position: stage input output n2 0 1 k - 1 n2 k - 1 1 0 0 1 n1-1 (n1 - 1)(k - 1) n2(n1 - 1) tap position: stage output input channel ramsey type ii interleaver/deinterleaver zero generate (reg) #: (reg) #: L64724tm_300.book page 9 friday, april 14, 2000 2:17 pm
7-10 the fec decoder pipeline the minimum separation at the interleaver output is b symbols for any two symbols that are separated by less than n symbols at the interleaver input. any burst of b < b errors inserted by the channel results in single errors at the deinterleaver output. the L64724 deinterleaver for dss has the following features: periodic deinterleaving maximum block length of 146 bytes deinterleaving depth of 13 7.3 reed-solomon decoder the reed solomon decoder is a forward error correction (fec) unit that looks at the check bytes that are appended to the data stream and either corrects any errors that it ?nds in the data stream or asserts the erroroutn pin when it cannot correct the data. 7.3.1 terms and concepts error correction code (ecc) devices have a speci?c lexicon associated with their ability to correct transmission messages. this section de?nes the terms used for variables in the reed-solomon module. the terms are used throughout this document. r check bytes the encoder generates and appends check bytes to the incoming message according to the reed-solomon error correction encoding. the decoder uses check bytes to locate and correct errors caused by transmission. the system designer speci?es the size of the check byte ?eld within the limitations. there are 16 check bytes for both dss/dvb modes. L64724tm_300.book page 10 friday, april 14, 2000 2:17 pm
reed-solomon decoder 7-11 d detection power detection power speci?es the maximum number of detectable errors. detection power has a minimum value of and a maximum value of r. k message length the message contains multiple bytes. the size of the message varies, depending on the code word length and the check bytes used, where k = n C r. m symbol size a data transfer contains multiple symbols. the symbol size, m, is 8 bits. n codeword length the variable n is the sum of the number of message bytes and the number of check bytes (k + r). the value of n is 204 for dvb; 147 for dss (includes the mpeg sync bit). t number of error corrections this variable is the maximum number of error corrections performed by the decoder. the value of t is 8. 7.3.1.1 forward error correction (fec) fec requires an encoder that appends redundant check bytes to a message before transmission. the check bytes, with an indeterminate number of bits, are referred to as symbols. the message symbols followed by redundant check symbols are called code words. the check symbols are redundant in the sense that they are derived from the message and are appended to the message. check symbols are also referred to as redundant check bytes, and sometimes as correction bytes. figure 7.7 illustrates a code word. explanatory text follows the ?gure. r 2 ---- L64724tm_300.book page 11 friday, april 14, 2000 2:17 pm
7-12 the fec decoder pipeline figure 7.7 code word structure a code word is a block of n bytes that includes k message symbols and n C k check bytes (r.) the check bytes or symbols are some fraction of the message symbols. a large number of check symbols allows the decoder to correct a large number of transmission errors. the redundant check symbols in a message allow a decoder at the receiving end of a transmission line to detect transmission errors and reconstruct the original message content. figure 7.8 shows a block diagram of the basic encoder and decoder functions in a transmission system. figure 7.8 fec data path after generating a code word, the encoder transmits it through a low cost channel to a decoder. the decoder compares the bit stream in the message data to the encoding in the check bytes to detect transmission errors. the original message can be precisely reconstructed from the check symbols, as long as the number of symbol errors in the code word is less than or equal to r/2. 7.3.1.2 reed-solomon error correction codes reed-solomon (rs) error correction codes are systematic and operate on bytes rather than single-bit data streams. they are especially good in burst error applications the importance of rs codes is illustrated by their adoption as international and domestic standards in various areas of n code word bytes k message bytes r redundant check bytes encoder decoder corrected channel message data message data message + check bytes = code word code word - check bytes = message L64724tm_300.book page 12 friday, april 14, 2000 2:17 pm
reed-solomon decoder 7-13 applications. the codes are expressed by convention as two numbers, the ?rst indicating the total codeword length (n), and the second indicating the number of message bytes (k). the difference between these two numbers (n C k) is the number of check bytes. a (255, 233) rs code, for instance, with 8-bit bytes, was adopted as part of the standard for space missions by both the european space agency and nasa. the compact disc digital-audio system uses a combination of a (32, 28) rs code and a (28, 24) rs code. the mil-std-2179/ansi x3b.6 media exchange standard uses a (161, 153) rs code and a (128, 118) rs code for high-density magnetic recording. the L64724 uses the following generator polynomial for rs codes: where a is a root of the binary primitive polynomial: a data byte (d 7 ,d 6 , .... d 1 ,d 0 ) is identi?ed with the element d 7 a 7 +d 6 a 6 + .... + d 1 a +d 0 in gf(256), the ?nite ?eld with 256 elements. the error correcting power of an rs code is related to the number of redundant check symbols in its code words. in general, an rs code with two t check symbols per code word can correct up to t byte errors per code word. higher redundancy allows more errors to be corrected the remainder of this section describes the process of correcting transmission errors with reed-solomon codes. 7.3.1.3 error handling and correction a bit error occurs when a transmitted zero is received as a one or vice versa. a byte error occurs when one or more bits in the byte have errors. for example, a byte with only one bit error is counted as one byte error, and a byte with m bit errors (all bits are inverted) is also counted as one byte error. as long as a code word has no more than t = byte errors, the rs decoder corrects all errors. when a code word has more than t = byte errors, the rs decoder detects the presence of excessive errors and asserts the erroroutn signal to notify the user. x a i + () i0 = r1 C ? x 8 x 4 x 3 x 2 1 ++++ r () 2 r () 2 L64724tm_300.book page 13 friday, april 14, 2000 2:17 pm
7-14 the fec decoder pipeline assume that the byte size is 8, the redundant check parameter is 32, and a 122-bit burst error is input to the rs decoder. the rs decoder can correct up to t = 16 byte errors. a 122-bit burst can be divided into 17 bytes as shown in figure 7.9 , where each e represents a one bit error. because the redundancy is 32, the decoder corrects up to 16 byte errors. because the 122-bit burst corrupts 17 consecutive bytes, the maximum guaranteed correctable burst length in this example is 121 bits. figure 7.9 122-bit burst example 7.3.2 features flag for corrected errors complies with ccitt-recommended ccir723 standard for digital tv transmission dvb/dss compliant decoder channel output counts for uncorrected data and error vector data erroroutn signal ?ags uncorrectable errors (204, 188) reed-solomon code format for dvb (146, 130) reed-solomon code format for dss eeeeeeeee . . . . . . eeeeeeee 1 byte 17 bytes 122 bits L64724tm_300.book page 14 friday, april 14, 2000 2:17 pm
descrambler module architecture and operation 7-15 7.3.3 performance analysis the performance of the code against independent random byte errors can be computed by the equation: equation 7.1 where: when more than t byte errors occur in a code word, the rs decoders usually detect the presence of excessive errors and raise the uncorrectable error ?ag to notify the user. however, there is a small probability that the erroneous decoded code word remains undetected. the undetected erroneous code word rate is: 7.4 descrambler module architecture and operation figure 7.10 shows a block diagram of the descrambler. the descrambler performs two functions: generates a pseudorandom binary sequence (prbs) that modi?es the incoming data stream properly aligns data with the prbs note: the descrambler module is used only in the dvb mode of operation. q i n ---- n i ? ?? p i 1 p C () ni C it 1 + = n ? = n = code word length in bytes p = input byte error rate t = number of errors to correct q = output byte error rate = binomial coef?cient that represents the number of ways of choosing i items from a collection of n distinct items n i ? ?? 1 t! ------ n 2 m 1 C ---------------- ? ?? t n i ? ?? p i 1 p C () ni C it 1 + = n ? L64724tm_300.book page 15 friday, april 14, 2000 2:17 pm
7-16 the fec decoder pipeline 7.4.1 prbs generation the block diagram of figure 7.10 shows the operation of the prbs. figure 7.10 descrambler block diagram the following generator polynomial produces the pseudorandom bit sequence in the descrambler: 7.4.2 data alignment with prbs the 15-bit shift register is initialized with a speci?c value, as shown in figure 7.11 . figure 7.11 15-bit shift register initialization : the encoder inverts every eighth mpeg transport sync word (0x47) to generate a sync word (0xb8) that the decoder then uses to align the descrambler with the incoming data stream. the ?rst bit of the prbs is applied to the ?rst data bit following the inverted mpeg sync byte. during the following seven noninverted mpeg sync words, the L64724 operates the descrambler sequence generator, but does not modify the data stream. the L64724 resets the descrambler after every inverted mpeg sync word (see figure 7.12 ). descrambled scrambled bit stream 12 3 4 5 6 7 8 9 10 11 12 13 14 15 shift register bit stream xor xor 1 x 14 x 15 ++ 12 3 4 5 6 7 8 9 10 11 12 13 14 15 shift register initialization sequence 10 010 10 10000000 L64724tm_300.book page 16 friday, april 14, 2000 2:17 pm
fec module software reset 7-17 figure 7.12 inverted sync words in descrambler 7.5 fec module software reset the L64724 resets the internal datapath and control modules for the fec portion of the device when the fec_rst bit (group 4, apr 55) is set to one. the demodulator module is not affected. you do not need to clear the bit back to zero to complete the reset. the L64724 issues a single reset pulse each time the microcontroller writes a one to the fec_rst bit. when the fec_rst bit is set, the L64724 resets the fec processing unit and state machines to their initial states. the following operations occur when the fec_rst bit is set to one: internal datapath and control modules reset group 4 registers unaffected by reset group 3 uec and cec counters reset dvalidout pin set low fstartout pin set low erroroutn pin set high sync byte 8 * 204 bytes inverted sync byte inverted sync byte 204 bytes L64724tm_300.book page 17 friday, april 14, 2000 2:17 pm
7-18 the fec decoder pipeline L64724tm_300.book page 18 friday, april 14, 2000 2:17 pm
L64724 satellite receiver 8-1 chapter 8 L64724 speci?cations this chapter provides the speci?cations for the L64724 satellite decoder from lsi logic. the L64724 is implemented in 3.3-volt hcmos. this chapter contains the following sections: section 8.1, electrical requirements section 8.2, ac timing section 8.3, L64724 packaging all speci?cations are preliminary and subject to change. 8.1 electrical requirements this section speci?es the electrical requirements for the L64724 device. four tables list electrical data in the following categories: absolute maximum ratings table 8.1 recommended operating conditions table 8.2 capacitance table 8.3 dc characteristics table 8.4 pin description summary table 8.5 L64724tm_300.book page 1 friday, april 14, 2000 2:17 pm
8-2 L64724 speci?cations table 8.1 L64724 absolute maximum rating (referenced to v ss ) symbol parameter limits 1 1. note that the ratings in this table are those beyond which permanent device damage is likely to occur. these values should not be used as the limits for normal device operation. unit v dd dc supply voltage - 0.3 to + 3.9 v v in lvttl input voltage - 1.0 to v dd + 0.3 v v in 5 v compatible input voltage - 1.0 to 6.5 v i in dc input current 10 ma t stg storage temperature range (plastic) - 40 to + 125 c table 8.2 L64724 recommended operating conditions symbol parameter limits 1 1. for normal device operation, adhere to the limits in this table. sustained oper- ation of a device at conditions exceeding these values, even if they are within the absolute maximum rating limits, may result in permanent device damage or impaired device reliability. device functionality to stated dc and ac limits is not guaranteed if conditions exceed recommended operating conditions. contact lsi logic for the package thermal impedance information for this chip. unit v dd dc supply voltage +3.0 to 3.6 v table 8.3 L64724 capacitance symbol parameter 1 1. measurement conditions are v in = 3.3 v, t a = 25 ?c, and clock frequency = 1 mhz. max units c in input capacitance 5 pf c out output capacitance 5 pf L64724tm_300.book page 2 friday, april 14, 2000 2:17 pm
electrical requirements 8-3 table 8.4 lists the dc characteristics of the L64724. table 8.4 dc characteristics of the L64724 symbol parameter 1 1. to identify an input with an internal pullup or pulldown resistor or an outputs drive strength, see table 8.5 . condition 2 2. speci?ed at vdd = 3.3 v 5% at ambient temperature over the speci?ed range. min typ max unit v dd supply voltage C 3.0 3.3 3.6 v v il input voltage low C v ss - 0.5 C 0.8 v v ih input voltage high lvttl com/ind/mil temp range 2.0 C v dd + 0.3 v 5-volt compatible 2.0 C 5.5 v v t switching threshold C C 1.4 2.0 v i il input current leakage v dd = max, v in =v dd or v ss - 10 110ma i ipu input current leakage w/pullup v in =v ss - 62 - 215 - 384 ma i ipd input current leakage w/pulldown v in =v dd - 62 - 215 - 384 ma v oh output voltage high i oh = - 1.0, - 2.0, - 4.0, - 6.0, - 8.0, - 12.0 ma 2.4 C v dd v v ol output voltage low i oh = 1.0, 2.0, 4.0, 6.0, 8.0, 12.0 ma C 0.2 0.4 v i oz 3-state output leakage current v dd = max, v out =v ss or 3.5 v - 10 110 m a i osp4 current p-channel output short circuit (4-ma output buffers) 3 3. not more than one output may be shorted at time for a maximum duration on one second. v out =v dd v out =v ss C C 140 - 40 ma i osp6 current p-channel output short circuit (4-ma output buffers) 3 v out =v dd v out =v ss C C 210 - 60 ma i dd quiescent supply current v in =v dd or v ss CC2ma L64724tm_300.book page 3 friday, april 14, 2000 2:17 pm
8-4 L64724 speci?cations table 8.5 L64724 pin description summary mnemonic description type a[2:0] address ttl input with pulldown 1 adcvddi/q adc power input adcvssi/q adc analog ground input adcvrefi/q adc reference input adcvrefni/q adc reference input asn address strobe ttl input with pullup 1 bclkout byte clock out output clk ivin/qvin input clock ttl input co[7:0] channel data out 3-state output coen channel output enable ttl input with pullup 1 csn chip select ttl input with pullup 1 d[7:0] data bidirectional ttl dtack/pol data acknowledge/wait polarity open drain output dtackn/wait data acknowledge/wait open drain output dvalidout valid data out cmos output erroroutn error detection flag 3-state output fstartout frame start output output host_mode serial or parallel interface select 2 input ibias current bias i input ibypass[5:0] i channel data ttl inputs iddtn test pin input intn interrupt open drain output ivin i channel data input lp2 input to vco input (sheet 1 of 2) L64724tm_300.book page 4 friday, april 14, 2000 2:17 pm
electrical requirements 8-5 lclk decimated clock output output pclk pll clock output output pllvdd pll power input pllvss pll ground input pllagnd pll analog ground input pwrp power control open drain output qbypass[5:0] q channel data ttl inputs qvin q channel data input read/write read/write strobe ttl input with pullup 1 reset reset ttl input vdd digital power supply input vss digital ground input xctr_in control input cmos input xctr_out[3:0] external controls cmos outputs xoin crystal oscillator in cmos input xoout crystal oscillator out cmos output 1. do not use pullup or pulldown signals for active edge timing. 2. serial mode is the recommended interface mode. lsi logic does not recommend parallel mode for new designs. table 8.5 L64724 pin description summary (cont.) mnemonic description type (sheet 2 of 2) L64724tm_300.book page 5 friday, april 14, 2000 2:17 pm
8-6 L64724 speci?cations 8.2 ac timing this section presents ac timing information of the L64724. during ac testing, high inputs are driven to 3.0 v and low inputs are driven at 0 v. for transitions between high, low, and invalid states, timing measurements are made at 1.5 v, as shown in figure 8.1 . figure 8.1 ac test load and waveform for standard outputs for 3-state outputs, timing measurements are made from the point at which the output turns on or off. an output is on when its voltage is greater than 1/2 v dd or less than 0.5 v. an output is off when its voltage is less than v dd C 0.5 v or greater than 0.5 v, as shown in figure 8.2 . figure 8.2 ac test load and waveforms for 3-state outputs the timing parameters shown in figures 8.3 through 8.7, refer to the numbers in column 1 of tables 8.6 through 8.9 . c l = 15 pf test output point 1.5 v 0.5 v v dd C 0.5 v 0.5 v 2.5 v i ref = - 20 ma i ref = 20 ma v ref = 1.5 v output test point 55 pf v ref L64724tm_300.book page 6 friday, april 14, 2000 2:17 pm
ac timing 8-7 figure 8.3 L64724 synchronous ac timing figure 8.4 L64724 reset timing diagram figure 8.5 L64724 bus 3-state delay timing inputs outputs clk 1 3 2 6 5 4 reset 7 8 coen co fstartout erroroutn 9 9 dvalidout bclkout L64724tm_300.book page 7 friday, april 14, 2000 2:17 pm
8-8 L64724 speci?cations figure 8.6 L64724 decoder read cycle figure 8.7 L64724 decoder write cycle cs d[7:0] as a[2:0] read dtackn valid valid 20 11 10 12 19 13 24 16 15 22 18 12 11 csn d[7:0] asn a[2:0] read dtackn valid valid 10 17 14 21 22 18 16 15 23 L64724tm_300.book page 8 friday, april 14, 2000 2:17 pm
ac timing 8-9 table 8.8 shows the timing parameters valid for operation with the internal microcontroller disabled. table 8.9 shows the timing for the microcontroller enabled. all parameters in the timing tables apply for t a =0 cto70 c and a capacitive load of 15 pf. table 8.6 L64724-75 ac timing parameters with microcontroller disabled parameter description register groups 75 mhz unit min max 1 t cycle clock cycle for clk C 13.3 C ns 2 t pwh clock pulse width high C 6.0 7.3 ns 3 t pwl clock pulse width low C 6.0 7.3 ns 4 t s input setup time to clk C0C ns 5 t h input hold to clk C4C ns 6 t od output delay from clk CC9 ns 7 t rwh reset pulse width high C 3 C clk cycles 1 8 t wk wake-up time C 280 C clk cycles 1 9 t dly delay from coen C C 15.0 ns 10 t surcs read setup before csn low C 0.0 C ns 11 t sua a[2:0] setup before asn low C 15.0 C ns 12 t hlda a[2:0] hold after asn low groups 0, 1, 4 groups 2, 3 0.0 0 Cns clk cycles 1 13 t dcsdtl data valid to dtackn/wait low groups 0, 1, 4 groups 2, 3 C 15.0 1 ns clk cycles 1 14 t hldd write data hold after csn high C 0.0 C ns (sheet 1 of 2) L64724tm_300.book page 9 friday, april 14, 2000 2:17 pm
8-10 L64724 speci?cations 15 t cycle_cs minimum csn width groups 0, 1, 4 groups 2, 3 45.0 5 Cns clk cycles 1 16 t hldrcs read hold after csn high C 0.0 C ns 17 t wrrec write recovery time groups 0, 1, 4 groups 2, 3 30.0 3 Cns clk cycles 1 18 t dcsdth csn high to dtackn/wait high groups 0, 1, 4 groups 2, 3 C 28.0 28.0 ns ns 19 t deld csn low to data valid groups 0, 1, 4 groups 2, 3 17.0 30.0 4 ns clk cycles 1 20 t dellz csn high to data 3-state groups 0-,4 14.0 24.0 ns 21 t sud data setup before csn change C 15.0 C ns 22 t hldw asn hold after csn low groups 0,1,4 groups 2,3 10.0 2 Cns clk cycles 1 23 t deldtl csn low to dtackn/wait low groups 0, 1, 4 groups 2, 3 C45 5 ns clk cycles 1 24 t rdrec read recovery time groups 0, 1, 4 groups 2, 3 30.0 5 Cns clk cycles 1 1. guaranteed by design. table 8.6 L64724-75 ac timing parameters with microcontroller disabled (cont.) parameter description register groups 75 mhz unit min max (sheet 2 of 2) L64724tm_300.book page 10 friday, april 14, 2000 2:17 pm
ac timing 8-11 table 8.7 L64724-75 ac timing parameters with microcontroller enabled parameter description register groups 75 mhz unit min max 1 t cycle clock cycle for clk C 13.3 C ns 2 t pwh clock pulse width high C 6.0 7.3 ns 3 t pwl clock pulse width low C 6.0 7.3 ns 4 t s input setup time to clk C 0C ns 5 t h input hold to clk C 4C ns 6 t od output delay from clk C C9 ns 7 t rwh reset pulse width high C 3 C clk cycles 1 8 t wk wake-up time C 280 C clk cycles 1 9 t dly delay from coen C C 15.0 ns 10 t surcs read setup before csn low C 0.0 C ns 11 t sua a[2:0] setup before asn low C 15.0 C ns 12 t hlda a[2:0] hold after asn low groups 0C4 0.0 C ns 13 t dcsdtl data valid to dtackn/wait low groups 0C4 C 7 ns + 1 cycle ns clk cycles 1 14 t hldd write data hold after csn high C 0.0 C ns 15 t cycle_cs minimum csn width groups 0C4 31 C clk cycles 1 16 t hldrcs read hold after csn high C 0.0 C ns 17 t wrrec write recovery time groups 0C4 5 C clk cycles 1 18 t dcsdth csn high to dtackn/wait high groups 0C4 C 28.0 ns 19 t deld csn low to data valid groups 0C4 17.0 28 clk cycles 1 20 t dellz csn high to data 3-state groups 0C4 14.0 24.0 ns 21 t sud data setup before csn change C 15.0 C ns 22 t hldw asn hold after csn low groups 0C4 2 C clk cycles 1 (sheet 1 of 2) L64724tm_300.book page 11 friday, april 14, 2000 2:17 pm
8-12 L64724 speci?cations 23 t deldtl csn low to dtackn/wait low groups 0C4 C 30 clk cycles 1 24 t rdrec read recovery time groups 0C4 5 C clk cycles 1 1. guaranteed by design. table 8.8 L64724-90 ac timing parameters with microcontroller disabled parameter description groups 1 90 mhz unit min max 1 t cycle clock cycle for pclk C 11.1 C ns 2 t pwh clock pulse width high C 5.25 6.1 ns 3 t pwl clock pulse width low C 5.25 6.1 ns 4 t s input setup time to clk C 0 C ns 5 t h input hold to clk C 4 C ns 6 t od output delay from clk C C 9 ns 7 t rwh reset pulse width high C 3 C clk cycles 2 8 t wk wake-up time C 280 C clk cycles 2 9 tdly delay from coen C C 15.0 ns 10 tsurcs read setup before csn low C 0.0 C ns 11 tsua a[2:0] setup before asn low C 15.0 C ns 12 thlda a[2:0] hold after asn low groups 0, 1, 4 groups 2, 3 0.0 0 Cns clk cycles 2 13 tdcsdtl data valid to dtackn/wait low groups 0, 1, 4 groups 2, 3 C 15.0 1 ns clk cycles 2 (sheet 1 of 2) table 8.7 L64724-75 ac timing parameters with microcontroller enabled (cont.) parameter description register groups 75 mhz unit min max (sheet 2 of 2) L64724tm_300.book page 12 friday, april 14, 2000 2:17 pm
ac timing 8-13 14 thldd write data hold after csn high C 0.0 C ns 15 tcycle_ cs minimum csn width groups 0, 1, 4 groups 2, 3 45.0 5 Cns clk cycles 2 16 thldrcs read hold after csn high C 0.0 C ns 17 twrrec write recovery time groups 0, 1, 4 groups 2, 3 30.0 3 Cns clk cycles 2 18 tdcsdth csn high to dtackn/wait high groups 0-4 C 28.0 ns 19 t deld csn low to data valid groups 0, 1, 4 groups 2, 3 17.0 30.0 4 ns clk cycles 2 20 t dellz csn high to data 3-state groups 0-4 14.0 24.0 ns 21 t sud data setup before csn change C 15.0 C ns 22 t hldw asn hold after csn low groups 0, 1, 4 groups 2, 3 10.0 2 Cns clk cycles 2 23 t deldtl csn low to dtackn/wait low groups 0, 1, 4 groups 2, 3 C45 5 ns clk cycles 2 24 t rdrec read recovery time groups 0, 1, 4 groups 2, 3 30.0 5 Cns clk cycles 2 1. the groups referred to are the register groups. 2. guaranteed by design. table 8.8 L64724-90 ac timing parameters with microcontroller disabled (cont.) parameter description groups 1 90 mhz unit min max (sheet 2 of 2) L64724tm_300.book page 13 friday, april 14, 2000 2:17 pm
8-14 L64724 speci?cations table 8.9 L64724-90 ac timing parameters with microcontroller enabled parameter description groups 1 90 mhz unit min max 1 t cycle clock cycle for pclk C 11.1 C ns 2 t pwh clock pulse width high C 5.25 6.1 ns 3 t pwl clock pulse width low C 5.25 6.1 ns 4 t s input setup time to clk C 0 C ns 5 t h input hold to clk C 4 C ns 6 t od output delay from clk C C 9 ns 7 t rwh reset pulse width high C 3 C clk cycles 2 8 t wk wake-up time C 280 C clk cycles 2 9 t dly delay from coen C C 15.0 ns 10 t surcs read setup before csn low C 0.0 C ns 11 t sua a[2:0] setup before asn low C 15.0 C ns 12 t hlda a[2:0] hold after asn low groups 0C4 0.0 C ns 13 t dcsdtl data valid to dtackn/wait low groups 0C4 C 7 ns + 1 cycle ns clk cycles 2 14 t hldd write data hold after csn high C 0.0 C ns 15 t cycle_cs minimum csn width groups 0C4 31 C clk cycles 2 16 t hldrcs read hold after csn high C 0.0 C ns 17 t wrrec write recovery time groups 0C4 5 C clk cycles 2 18 t dcsdth csn high to dtackn/wait high groups 0C4 C 28.0 ns (sheet 1 of 2) L64724tm_300.book page 14 friday, april 14, 2000 2:17 pm
L64724 packaging 8-15 8.3 L64724 packaging the L64724-75 is available in a 100-pin pqfp package. the L64724-90 is available in a 100-pin mqfp package. table 8.10 lists ordering information for the L64724. the tables and ?gures that follow provide a pinout and a mechanical drawing for the package. 19 t deld csn low to data valid groups 0C4 17.0 28 clk cycles 2 20 t dellz csn high to data 3-state groups 0C4 14.0 24.0 ns 21 t sud data setup before csn change C 15.0 C ns 22 t hldw asn hold after csn low groups 0C4 2 C clk cycles 2 23 t deldtl csn low to dtackn/wait low groups 0C4 C 30 clk cycles 2 24 t rdrec read recovery time groups 0C4 5 C clk cycles 2 1. the groups referred to are the register groups. 2. guaranteed by design. table 8.9 L64724-90 ac timing parameters with microcontroller enabled (cont.) parameter description groups 1 90 mhz unit min max (sheet 2 of 2) table 8.10 L64724 ordering information order number clock frequency (mhz) package type operating range 65035a2-002 75 100-pin pqfp commercial 65035a1-004 90 100-pin mqfp commercial L64724tm_300.book page 15 friday, april 14, 2000 2:17 pm
8-16 L64724 speci?cations 8.3.1 L64724 pinout figure 8.8 gives the pinout for the 100-pin pqfp/mqfp L64724 package. figure 8.8 100-pin pqfp/mqfp pinout vss vdd pllvss lp2 pllagnd pllvdd pclk lclk vss vdd a[1] a[2] read csn vss vdd asn dtack/waitn intn co[0] vss vdd co[1] co[2] co[3] vss vdd co[4] co[5] co[6] top view 97.L64724.ud 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 30 2 4 6 8 10 12 14 16 18 20 22 24 26 28 81 83 85 87 89 91 93 95 97 99 82 84 86 88 90 92 94 96 98 100 50 48 46 44 42 40 38 36 34 32 49 47 45 43 41 39 37 35 33 31 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 80 52 54 56 58 60 62 64 66 68 70 72 74 76 78 a[0] d[7] d[6] vdd vss d[5] d[4] d[3] d[2] vdd vss d[1] d[0] xctr_out0 xctr_out[1] xctr_out[2] vdd vss xctr_out{3] pwrp xctr_in dtack_pol qbias adcvrefq adcvrefqn adcvddq adcvssq qvin ibias adcvrefi adcvrefin adcvddi adcvssi ivin vdd vss host_mode ibypass[5] ibypass[4] ibypass[3] vdd vss ibypass[2] ibypass[1] ibypass[0] vdd vss qbypass[5] qbypass[4] qbypass[3] co[7] vss vdd xoout xoin vss clk vdd bclkout dvalidout fstartout erroroutn reset iddtn coen qbypass.0 vss vdd qbypass[1] qbypass[2] L64724tm_300.book page 16 friday, april 14, 2000 2:17 pm
L64724 packaging 8-17 8.3.2 mechanical drawings figure 8.9 is a mechanical drawing for the 100-pin pqfp/mqfp L64724-75 package. note: the L64724-75 is available in a pqfp package and can be used for applications that implement data rates of up to 31 mbaud and sampling frequencies of up to 75 mhz. for applications that require higher data rates, with sampling frequencies up to 90 mhz, the L64724-90 is available in an mqfp package. figure 8.9 100-pin pqfp/mqfp mechanical drawing for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code ud. md97.ud-1 L64724tm_300.book page 17 friday, april 14, 2000 2:17 pm
8-18 L64724 speci?cations figure 8.9 100-pin pqfp/mqfp mechanical drawing (cont.) for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code ud. md97.ud-2 L64724tm_300.book page 18 friday, april 14, 2000 2:17 pm
L64724 satellite receiver a-1 appendix a programming the L64724 using the serial bus protocol this appendix discusses how to program the L64724 internal registers and data tables in serial host interface mode. this chapter is intended primarily for system programmers who are developing software drivers using the serial bus. this chapter contains the following sections: section a.1, serial bus protocol overview section a.2, programming the slave address using the serial bus interface section a.3, write cycle using the serial bus interface section a.4, read cycle using the serial bus interface L64724tm_300.book page 1 friday, april 14, 2000 2:17 pm
a-2 programming the L64724 using the serial bus protocol a.1 serial bus protocol overview the multimaster serial bus interface has two signal linesd[1] (serial data) and d[0] (serial clock)that are connected to the bus as shown in figure a.1 . external pullup resistors are required to hold the bus high when the bus is not in operation. figure a.1 serial bus architecture serial host interface mode is selected when the host_mode input pin is deasserted (low). in serial host interface mode, data is transferred on the d[1] pin, synchronized to a serial clock that is input on the lsb of the host data bus, d[0]. the serial data clock can have a maximum frequency of 400 khz. the host data bus pins d[3:2] are used to input the two lsbs of the slave address, which the serial bus protocol requires. the slave address de?nition is shown below: figure a.2 7-bit slave address for the L64724 serial bus the bus master always generates the clock and cycle start and stop conditions. figure a.3 gives an overview of the read and write cycles using the serial bus protocol. d[1] d[0] 5.0 v serial bus compliant device serial bus compliant device 0 0 0 1 1 d[3] d[2] L64724tm_300.book page 2 friday, april 14, 2000 2:17 pm
serial bus protocol overview a-3 figure a.3 serial bus write/read cycle overview bit7 bit6 bit5 bit4 bit3 bit1 bit2 r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 d[1] d[0] start condition bit7 bit6 bit5 bit4 bit3 bit1 bit2 r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 d[1] master-transmitter, slave-receiver (master transmits slave address) ack cycle: slave master-transmitter, slave-receiver (master transmits data to slave) ack cycle: slave master-transmitter, slave-receiver (master transmits slave address) ack cycle: slave ack cycle: mas ter bit7 bit6 bit5 bit4 bit3 bit1 bit2 r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 d[1] master-transmitter, slave-receiver (master transmits slave address) ack cycle: slave ack cycle: master stop condition master-receiver, slave-transmitter (slave transmits data to master) master-receiver, slave-transmitter (slave transmits data to master) stop condition bit7 write cycle read cycle(burst) single-read cycle start condition: the master (drives d[0]) indicates the start of a cycle by pulling d[1] low when d[0] is high. stop condition: the master (drives d[0]) indicates the end of a cycle by releasing d[1] high when d[0] is high. data transfer: all data changes on the d[1] line occur only when clock is low, except for the special cases outlined above to acknowledge: the receiver always generates the acknowledge. in the case of a single read, the master-receiver does not generate indicate start/stop cycles. an ack so that it can generate the stop condition (as indicated above). L64724tm_300.book page 3 friday, april 14, 2000 2:17 pm
a-4 programming the L64724 using the serial bus protocol a.2 programming the slave address using the serial bus interface a general call address operation on the serial bus is indicated when the master generates a start condition followed by eight zeroes (see figure a.4 .) a general call address operation addresses every device on the serial bus. any device that requires information to be supplied through this general call structure should acknowledge the cycle (see figure a.3 .) the second byte, when set to 0b00000110, indicates a reset and a hardware write of the programmable part of the slave address. the L64724 must read the d[3:2] pins, which form the two lsbs of the slave address. the d[3:2] pins are unused when the serial interface is in use, and can be hardwired to any of the four possible combinations. figure a.4 general call structure a.3 write cycle using the serial bus interface refer to figure a.5 for a burst or a single write cycle. the following steps must take place for a write cycle: 1. the master starts the cycle with the start condition. 2. the master transmits the 7-bit slave address. 3. the master transmits the eighth bit (r/w) cleared to 0 to indicate a write cycle. 4. the addressed slave acknowledges the reception of the slave address by deasserting d[1] (low) in the ack cycle. 5. the master sends the 8-bit group 0 address (0x0) to indicate that the apr is to be loaded. group 0 is accessed only to load the apr. 0000 00 00 x a xxxx x ax0 s general call addr. s: start condition a: acknowledge cycle L64724tm_300.book page 4 friday, april 14, 2000 2:17 pm
write cycle using the serial bus interface a-5 6. the master sends the 8-bit data, which initializes the address pointer register (apr0/1). 7. the master generates another start condition. 8. the master repeats steps 2C7 to address the appropriate group and write one or more data bytes. 9. the master issues a stop condition to terminate the cycle. L64724tm_300.book page 5 friday, april 14, 2000 2:17 pm
a-6 write cycle using the serial bus interface figure a.5 burst write or single write to slave (master-transmitter, slave-receiver) start condition d[1] d[0] start condition 7-bit slave addr. r/w ack (slave) 8-bit group address ack (slave) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 d[1] 7-bit slave addr. ack (slave) 8-bit group address ack (slave) data 8-bit data 8-bit ack (slave) ack (slave) stop condition 8-bit data ack (slave) 1 2 3 4 5 6 7 8 9 note: the numbers in this ?gure refer to the steps listed under section a.3, write cycle using the serial bus interface. L64724tm_300.book page 6 friday, april 14, 2000 2:17 pm
read cycle using the serial bus interface a-7 a.4 read cycle using the serial bus interface please refer to figure a.6 for a burst or a single read cycle. the following steps must take place for a read cycle: 1. the master starts the cycle by issuing a start condition. 2. the master transmits the 7-bit slave address. 3. the master sets the r/w bit = 0 to indicate a write cycle. 4. the addressed slave acknowledges the reception of the slave address by driving d[1] low in the ack cycle. 5. the master sends the 8-bit group 0 address (0x0) to indicate that the apr is to be loaded. group 0 is accessed only to load the apr. 6. the master then sends the 8-bit data. this data is used to initialize the base pointer (apr0/1). 7. the master does a repeat start condition. 8. the master transmits the 7-bit slave address. 9. the master sets the r/w bit = 0 to indicate a write cycle. 10. the addressed slave acknowledges the reception by driving d[1] low in the ack cycle. 11. the master transmits the number of the group that it wishes to read (which is acknowledged by the slave). 12. the master issues another start condition. 13. the master transmits the 7-bit slave address. 14. the master sets the r/w bit = 1 to indicate a read cycle. 15. the slave drives d[1] low to acknowledge. 16. the slave starts transmitting the data, msb ?rst. 17. the master has to provide the acknowledge by driving d[1] low during the ack cycle. 18. in the case of a single read, the master does not drive d[1] low during the ack cycle after reception of the ?rst byte. the slave responds to this by relinquishing control of the bus and waiting for the master to issue a stop condition. for burst reads, the master drives d[1] low for each byte it receives during the ack cycle, except for the last byte. 19. the master terminates the cycle by issuing a stop condition. L64724tm_300.book page 7 friday, april 14, 2000 2:17 pm
a-8 read cycle using the serial bus interface figure a.6 burst read or single read cycle from slave start condition start condition d[1] d[0] start condition r/w ack (slave) 8-bit group address ack (slave) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit bit 0 bit 7 bit 6 bit 5 d[1] 7-bit slave ack (slave) ack (slave) r/w data 8-bit ack (slave) ack (master) stop condition 8-bit data ack (slave) addr. 8-bit group address 7-bit slave addr. r/w 7-bit slave addr. 1 6 5 4 3 2 7 13 12 10 9 8 11 14 15 16 17 18 19 note: the numbers in this ?gure refer to the steps listed under section a.4, read cycle using the serial bus interface. L64724tm_300.book page 8 friday, april 14, 2000 2:17 pm
L64724 satellite receiver b-1 appendix b L64724 application notes this appendix provides updated information on the use of the lsi logic L64724 satellite receiver in a typical application. it contains the following sections: section b.1, L64724 qpsk demodulator acquisition and debugging tips, describes how to program and monitor the L64724s agc, clock synchronization, and carrier synchronization loops. section b.2, demodulator con?guration tips, gives useful hints on selecting crucial parameters such as sampling frequency, decimation ?lter con?guration, and loop bandwidths. section b.3, qpsk demodulator and fec con?guration example: high data rates, shows an example of how the demodulator and fec portion of the L64724 can be programmed for high data rates. section b.4, qpsk demodulator and fec con?guration example: low data rates, shows an example of how the demodulator and fec portion of the L64724 can be programmed for low data rates where the oversampling ratio is greater than four. also, refer to the L64724 satellite receiver evaluation board users guide, which gives a good description of board related issues and demodulator and fec programming guidelines. b.1 L64724 qpsk demodulator acquisition and debugging tips this section presents a debugging procedure to follow in case the L64724 qpsk demodulator fails to lock. L64724tm_300.book page 1 friday, april 14, 2000 2:17 pm
b-2 L64724 application notes b.1.1 automatic gain control (agc) loop the agc loop must lock ?rst. when the agc loop is closed, the signal level at the analog-to-digital converter (adc) input is 0.588 (1/1.7) times the adc range, assuming the pwr_ref register (group 4, apr 24) is set to its correct value and df_gain = 1. a simple test that you can perform is to change the power of the transmitted signal and observe the i or q channels with an oscilloscope just before the adc input. make sure that the peak-to-peak signal range is about 1/1.7 of the peak-to-peak adc range. also check that the agc can keep the signal level ?xed, even when the transmitted power is changed. observe that the agc voltage at the loop output is changing with the changes in the transmitted power. you may need to toggle the pwrp bit (group 4, apr 54) to switch the polarity of the pwrp output. the parameters in the following subsections are related to the agc loop. b.1.1.1 group 4, apr 21set to 0x00 clear the pll_bp bit to 0 to enable the internal pll to generate the a/d clock. clear the clk_div1[4:0] bits to 0 because the internal pll is used. set group 4, apr 21 to 0x00. b.1.1.2 group 4, apr 21C23set to 0x00 set group 4 apr 21 and 23 to 0x00, because the clk_div bits are unused when the internal pll has been selected. b.1.1.3 group 4, apr 24 the pwr_ref[7:0] parameter controls the signal level at the input of the adc. it should be set to the value given in equation 5.26, on page 5-21 . b.1.1.4 group 3, apr 10 the pwr_lvl[7:0] ?eld is proportional to the mean value of the agc level. with an agc ampli?cation range of 0 db to - 40 db, ta b l e b . 1 shows the corresponding pwr_lvl settings and ampli?cation levels. L64724tm_300.book page 2 friday, april 14, 2000 2:17 pm
L64724 qpsk demodulator acquisition and debugging tips b-3 b.1.1.5 group 4, apr 26 the scale[7:0] parameter controls the internal signals demi and demq. it does not affect the loop itself, but it is related to pwr_ref by equation b.1 . equation b.1 if pwr_ref = 84, scale = 186 (for e s /n o = 4 db). b.1.1.6 pwrp pin connect the L64724 pwrp output pin to 5 volts using a 470-ohm pullup resistor. the pwrp pin is then connected to an rc loop ?lter with a time constant of ~60 microseconds. figure b.1 shows how to connect the pwrp pin to the agc circuit. figure b.1 agc loop control for more information on the agc loop, see section 5.8, automatic gain control (agc), page 5-20 . table b.1 pwr_lvl register setting pwr_lvl setting ampli?cation (db) 00 128 C20 255 C40 scale 2047 1 e s n o ------- ? ?? 1 C + 2 pwr ref C -------------------------------------------------- = v agc r agc ~ 2.7 k c agc ~ 22 nf n p pwr r ~ 470 w 5 v L64724tm_300.book page 3 friday, april 14, 2000 2:17 pm
b-4 L64724 application notes b.1.2 clock loop set the loop bandwidth according to equation 5.8 ,on page 5-10 . the clk_lcf status bit (group 3, apr 11, bit 3) indicates whether the clock loop is locked. b.1.3 carrier loop the following steps show how to set up the carrier loop. 1. set the car_sw bit to 1 the and car_open bit to 0 in the carrier loop con?guration register (group 4, apr 41). these bit settings force the sweep to begin. auto sweep can be selected to sweep between upper and lower sweep limits. 2. change the upper and lower sweep limits registers (car_uswl and car_lswl in group 4, apr 34C37) and observe car_ncof (group 3, apr 7). 3. change the value in the carrier sweep rate register (car_swr in group 4, apr 32 and 33). if the sweep rate is fast, you may not be able to turn the sweep off fast enough through manual intervention, the microcontroller will have to do this in real time. b.1.4 qpsk demodulator debugging summary the following steps summarize how to debug the qpsk demodulator portion of a system that includes the L64724. 1. ensure that the agc loop functions properly. 2. ensure that the clock loop is locked. 3. set the car_sw and car_open bits in the carrier loop con?guration register to 0b01. the loop should now lock or at least slow down near the center of the frequency range. 4. if the carrier still does not lock, check the car_swp parameter and recalculate the loop constant values if needed. each one of these parameters affects the behavior of the loop. 5. if the carrier seems to lock and stops sweeping, check the carrier and fec synchronization status register (group 3, apr 11) for the status. all ?ags should be set to 1 when the carrier and clock are locked. L64724tm_300.book page 4 friday, april 14, 2000 2:17 pm
demodulator con?guration tips b-5 6. if all of the ?ags in the carrier and fec synchronization status register are set to 1, clear the car_sw bit in the carrier loop con?guration register to 0b0. the sweep turns off. b.2 demodulator con?guration tips the following tips help in con?guring the demodulator registers. refer to the L64724 satellite receiver evaluation board users guide. the acquisition process is controlled by the L64724 microcontroller. for the equations given in the following subsections, the relationship shown in equation b.2 holds. equation b.2 b l is the loop bandwidth, w n is the natural frequency, and z is the damping factor. b.2.1 car_bw (carrier loop bandwidth) set the carrier loop bandwidth according to equation b.3 . equation b.3 car_bw b.2.2 car_swr (carrier sweep rate) to provide reliable acquisition at any signal-to-noise ratio, the microcontroller uses two sweep rates. the fast rate pulls the loop out of false locks. the parameters in the above table might have to be adjusted at very low rates (< 2 msps) for optimal performance, depending on the tuner. the sweep rate equations are shown in equation b.4 . equation b.4 b l zw n 2 --------- - 1 1 4 z 2 -------- - + ? ?? = carrier_bw (khz) rs(msps) = slow_sweep_rate[mhz/s] n x rs ms/s [] = fast_sweep_rate[mhz/s] m x rs ms/s [] = L64724tm_300.book page 5 friday, april 14, 2000 2:17 pm
b-6 L64724 application notes rs is the symbol rate and m and n are as shown in the following table. b.2.3 sym_bw (timing loop bandwidth) equation b.5 describes the timing loop bandwidth. equation b.5 b.2.4 sym_swr (timing loop sweep rate) equation b.6 describes the timing loop sweep rate. equation b.6 rs (ms/s) 1 1. megasamples per second. mn 45 to 15 32 8 15 to 7.5 8 2 7.5 to 3.75 8 1 3.75 to 2 8 1 2to1 4 1 symbol_bw (khz) rs(ms/s) /10 = symbol_sweep_rate (khz/s) 0.1 * slow_sweep_rate (mhz/s) = L64724tm_300.book page 6 friday, april 14, 2000 2:17 pm
demodulator con?guration tips b-7 b.2.5 decimation control the decimation and the sampling rate are con?gured to provide the highest possible number of samples per symbol with the tightest decimation ?lter available. the procedure is outlined in ta b l e b . 2 and the results are shown in ta b l e b . 3 . table b.2 decimation procedure rs threshold (ms/s) 1 1. megasamples per second (ms/s) df_ratio df_select df_gain group 4, register 19 setting fs (mhz) binary hex 45 to 44.5 1 0 1 10000100 0x84 91.5 (n = 1, s = 61, t=10,m=3 44.5 to 30 1 0 1 10000100 0x84 see footnote 2 2. for rs <= 44.5 msps, calculate the sampling rate as follows: from the set of valid sampling frequency values, (30, 35, 40 ..., 85, 90), select the lower, closest value to 4 * df_ratio * rs/(1 + alpha), where alpha is the corner margin (1%). 30 to 15 1 1 1 00000100 0x04 see footnote 15 to 7.5 2 2 2 00101000 0x28 see footnote 7.5 to 3.75 4 3 4 01010001 0x51 see footnote 3.75 to 1 8 4 8 01111010 0x7a see footnote table b.3 decimation results rs (ms/s) 1 sampling frequency (mhz) df_ratio samples per symbol df_filter df_gain 45 91.5 1 2.033 0 1 44.5 90 1 2.022 0 1 44 90 1 2.045 0 1 43 90 1 2.093 0 1 42 90 1 2.143 0 1 41 90 1 2.195 0 1 (sheet 1 of 3) L64724tm_300.book page 7 friday, april 14, 2000 2:17 pm
b-8 L64724 application notes 40 90 1 2.250 0 1 39 90 1 2.308 0 1 38 90 1 2.368 0 1 37 90 1 2.432 0 1 36 90 1 2.500 0 1 35 90 1 2.571 0 1 34 90 1 2.647 0 1 33 90 1 2.727 0 1 32 90 1 2.813 0 1 31 90 1 2.903 0 1 30 90 1 3 000 1 1 29 90 1 3.103 1 1 28 90 1 3.214 1 1 27 90 1 3.333 1 1 26 90 1 3.462 1 1 25 90 1 3.600 1 1 24 90 1 3.750 1 1 23 90 1 3.913 1 1 22.7250 85 1 3.740 1 1 21.4625 80 1 3.727 1 1 20.2000 75 1 3.713 1 1 18.9375 70 1 3.696 1 1 17.6750 65 1 3.678 1 1 16.4125 60 1 3.656 1 1 15.1500 55 1 3.630 1 1 15 90 2 6.000 2 2 14 90 2 6.429 2 2 13 90 2 6.923 2 2 12 90 2 7.500 2 2 11.3625 85 2 7.481 2 2 10.7313 80 2 7.455 2 2 10.1000 75 2 7.426 2 2 table b.3 decimation results (cont.) rs (ms/s) 1 sampling frequency (mhz) df_ratio samples per symbol df_filter df_gain (sheet 2 of 3) L64724tm_300.book page 8 friday, april 14, 2000 2:17 pm
demodulator con?guration tips b-9 9.4688 70 2 7.393 2 2 8.8375 65 2 7.355 2 2 8.2063 60 2 7.312 2 2 7.5750 55 2 7.261 2 2 7.5 90 4 12.000 3 4 7 90 4 12.857 3 4 6 90 4 15.000 3 4 5.6813 85 4 14.961 3 4 5.3656 80 4 14.910 3 4 5.0500 75 4 14.851 3 4 4.7344 70 4 14.785 3 4 4.4188 65 4 14.710 3 4 4.1031 60 4 14.623 3 4 3.7875 55 4 14.521 3 4 3.75 90 8 24.000 4 8 3 90 8 30.000 4 8 2.8406 85 8 29.923 4 8 2.6828 80 8 29.819 4 8 2.5250 75 8 29.703 4 8 2.3672 70 8 29.571 4 8 2.2094 65 8 29.420 4 8 2.0516 60 8 29.246 4 8 1.8938 55 8 29.043 4 8 1.7359 50 8 28.803 4 8 1.5781 45 8 28.515 4 8 1.4203 40 8 28.163 4 8 1.2625 35 8 27.723 4 8 1.1047 30 8 27.157 4 8 1 30 8 30.000 4 8 1. megasamples per second table b.3 decimation results (cont.) rs (ms/s) 1 sampling frequency (mhz) df_ratio samples per symbol df_filter df_gain (sheet 3 of 3) L64724tm_300.book page 9 friday, april 14, 2000 2:17 pm
b-10 L64724 application notes b.3 qpsk demodulator and fec con?guration example: high data rates this section gives an example of how to use the microcontroller interface of the L64724 to con?gure the qpsk demodulator and fec section for high data rates. no decimation or decimation ?ltering is performed. the con?guration in the example is optimized for ?xed rate operation with the following parameters: the registers for this example are con?gured as shown in the following subsections. see ta b l e b . 8 ,on page b-26 , for a summary of the register settings. group 4, apr 0 C set to 0x81. set bit d7 to 1 and clear bit d6 to 0. based on section 4.2, set the pll_n[5:0] bits (d5 to d0) to 0x01. group 4, apr 1 C set to 0x14. clear bits d7 and d6 to 0. based on section 4.2, set pll_s[5:0] (d5 to d0) to 0x14. parameter value transmission rate 42.6 mbit/s (21.3 mbaud) adc sampling frequency 50 mhz xtal osc 15.00 mhz adc input: 1.0 v p-to-p dc offset control used after a/d, not after nyquist ?lter. viterbi rate 1/2 e b /n o 4.0 db model dvb L64724tm_300.book page 10 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: high data rates b-11 group 4, apr 2 C set to 0x06. set the imq bit (d7) to either 0 or 1, clear the dvb_dss bit (d6) and the qb bit (d5) to 0. based on table 4.2, set pll_t[4:0] (d4 to d0) to 0x06. group 4, apr 3 C set to 0x18. clear the viterbi code rate[2:0] bits (d7 to d5) to 0 for rate 1/2, set the tei bit (d4) to 1, set the sync2_mod bit (d3) to 1, clear bit d2 to 0, and based on section 4.3, clear the pll_m[1:0] bits (d1 to d0) to 0. group 4, apr 4 C set to 0x40. since the viterbi code rate is 1/2, based on the graph shown in figure 6.4, for a e b /n o = 4.0 (e s /sigma^2 = 7.0), a choice of 0.24 for vmbec/vmdc1 establishes a valid decision threshold over the entire snr range. equation b.7 shows the relationship between vmbec and vmdc1. equation b.7 choosing vmdc1[7:0] = 64 (0x40) yields a value of 30 (0x1e) for vmbec[7:0]. group 4, apr 5C7 C set to 0x0f0000. the vmdc2[23:0] bits select a second window. the vmdc2[23:0] value controls the window size over which viterbi errors are counted. the vmdc2[23:0] value is used for calculating the ber, not for the auto-synchronization that is controlled by the vmdc1[7:0] bits. in this example, choose a window size of 3.932 x 10 6 bits = vmdc2[23:0] x 4, which is approximately equal to 0x0f0000 set group 4, apr 5 to 0x00, set group 4, apr 6 to 0x00, and set group 4, apr 7 to 0x0f. 0.24 128 vmbec 32 + 256 vmdc 1 ---------------------------------------------- = L64724tm_300.book page 11 friday, april 14, 2000 2:17 pm
b-12 L64724 application notes group 4, apr 8 C set to 0x1e. equation b.7 yields a value for vmbec[7:0] of 30 (0x1e.) group 4, apr 9, 10, 11, 12, 13 C set all these registers to 0x00. group 4, apr 14 C set to 0x47. the dvb synchronization word[7:0] value is 0x47. group 4, apr 15 C set to 0x00. clear d7 to 0. clear the auto rate bit (d6) to 0 to obtain a code rate from the viterbi code rate. clear the d5 and d4 bits to 0. clear the imq_en bit (d3) to 0 for imq to be determined by apr 2 bit 7. clear the di_bypass bit (d2) to 0 to enable the deinterleaver, and clear the l[1:0] bits (d1and d0) to 0 to select zero mismatching bits. group 4, apr 16 C set to 0x00. clear the d7 and d6 bits to 0. clear the sss[1:0] bits (d5 and d4) to 0 to observe viterbi decoder sync. clear the ssa[1:0] bits (d3 and d2) to 0 to set the number of sync words to acquire to three. clear the sst[1:0] bits (d1 and d0) to 0 to set the number of missed sync words until loss of lock is equal to two. group 4, apr 17 C set to 0x00. clear d7 and d6 to 0. clear the of bit (d5) to 0 for serial mode and clear the os[4:0] bits (d4 to d0) to 0 to observe the descrambler output. group 4, apr 18 C set to 0x00. write any value to this register to reset the pll module. L64724tm_300.book page 12 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: high data rates b-13 group 4, apr 19 C set to 0x84. select the register bits according to the following table. a df gain of one is chosen because no decimation ?lter was used. group 4, apr 20 C set to 0x01. clear bits d7 through d5 to 0. clear the pd bit (d4) to 0 for normal operation. clear bits d3 to d1 to 0. set the mf_20_35 bit (d0) to 1 for a matched ?lter roll-off factor of 0.35. group 4, apr 21 C set to 0x00. clear the pclk_inv bit (d7) to 0 for a non-inverted pclk output. clear the pll_bp bit (d6) to 0 to enable the internal pll to generate the a/d clock. clear the lclk_off bit (d5) to 0 to turn off the lclk signal. clear the clk_div1[4:0] bits (d4 to d0) to 0 because the internal pll is used. group 4, apr 22 C set to 0x00. set apr register 22 to 0x00, because the clk_div2[7:0] bits are unused when the internal pll has been selected. group 4, apr 23 C set to 0xc0. set the dc_offset_on_off[1] bit (d7) to 1 to cause the dc offset compensation after the adc to be activated. set the dc_offset_on_off[0] bit (d6) to 1 to cause the noise feedback to the compensation circuit to be selected. clear the d5 bit to 0. clear the clk_div2[12:8] bits (d4 to d0) to 0, because the clk_div2[12:8] bits are unused when the internal pll has been selected. bits setting parameter meaning d7 to d5 0b100 df_select [2:0] no decimation ?lter selected. d4 to d3 0b00 df_gain[1:0] df gain = 1 (no decimation ?lter used). d2 to d0 0b100 df_ratio[2:0] no decimation implemented. L64724tm_300.book page 13 friday, april 14, 2000 2:17 pm
b-14 L64724 application notes group 4, apr 24 C set to 0x54. set the pwr_ref[7:0] bits to 0x54. see section 5.8.1, adc range and power reference, page 5-20 , for more details. group 4, apr 25 C set to 0x00. clear the d7 to d3 bits to 0. clear the int_dc bit (d2) to 0 to disable internal dc offset compensation after the matched ?lter and clear the pwr_bw[1:0] bits (d1 and d0) pwr_bw to 0 (see section 5.8.2, power control loop, page 5-21 .) group 4, apr 26 C set to 0xba. use equation b.8 to calculate the value of scale[7:0]. equation b.8 group 4, apr 27 C set to 0x64. this register is set to a signal-to-noise threshold value dependent on the value of the pwr_ref[7:0] value. the snr_ths[7:0] bits contain a threshold value that indicates a good or bad signal-to-noise ratio. set the snr_ths[7:0] value to 100 (0x64.) group 4, apr 28 C set to 0xaa. this register defines the loop bandwidths for a particular baud rate (in the equations that follow, the symbol t represents the baud period). a good approximation to the equivalent noise bandwidth is given in equation b.9 (for high data rates). the damping factor ( z) is chosen as 1.0. k dcar = k digital x 0.78/32.0. k digital is chosen from table 5.4 ,on page 5-19 .fora snr of 4db, k digital = 10, with the result that k dcar = 0.24. using these values, we get l car = fs/fb = 50e6/21.3e6 = 2.34. scale 2047 1 e s n o ------- ? ?? 1 C + 2 pwr_ref -------------------------------------------------- = scale 2047 1 2.51 () 1 C + 284 ----------------------------------------------------- 186 == (0xba) L64724tm_300.book page 14 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: high data rates b-15 equation b.9 for a baud rate of 21.3 mbaud we can choose b l = 66 krad/s and therefore w n = 106 krad/s. the loop equations are calculated as shown in equation b.10 and equation b.11 . equation b.10 equation b.11 the values of t a and t b are used to calculate car_mu_sel[3:0] and car_lambda_sel[3:0] registers in group 4. we can now calculate t a and t b as shown in equation b.12 and equation b.13 . equation b.12 equation b.13 car_mu_sel[3:0] and car_lambda_sel[3:0] are de?ned in equation b.14 and equation b.15 . equation b.14 b l 0.003125 baudrate = b l zw n 2 --------- - 1 1 4 z 2 -------- - + ? ?? = t a w n 2 t 2 k dcar l car -------------------------- - 2 p = t b 2 zw n t k dcar l car -------------------------- - 2 p = t a 106 10 3 () 2 1 21.3 10 6 -------------------------- - ? ?? 2 0.24 2.34 --------------------------------------------------------------------- - 44 10 6 C == t b 2 106 10 3 1 21.3 10 6 -------------------------- - 0.24 2.34 -------------------------------------------------------------------- - 17.7 10 3 C == car_mu_sel l og 2 t ( a 2 25 ) log 2 44 e -6 2 25 ) ( = 10 = 0xa = = L64724tm_300.book page 15 friday, april 14, 2000 2:17 pm
b-16 L64724 application notes equation b.15 program the four lsbs of apr 28 with 0xa and the four msbs of apr 28 with 0xa. group 4, apr 29 C set to 0x1f. the recommended value for car_lc_thsl[7:0] is 31 (0x1f) when fp_lock_len (group 4, apr 54) is set to 0. otherwise, set it according to the following table: group 4, apr 30 C set to 0x00. group 4, apr 31 C set to 0x20. set the rs bit/byte select bit (d7) as needed to select the reed- solomon bit or byte error count for group 3 apr 0 and 1. set the errorout_invert bit (d6) as needed to control the polarity of the erroroutn signal. set the spi_on_off bit (d5) to 1. clear bits d4 through d0 to 0. group 4, apr 32C33 C set to 0x6ae. the value for the sweep rate, car_swr[15:0], is set according to equation b.16 , equation b.17 and equation b.18 . equation b.16 equation b.17 fp_lock_len car_lc_thsl[7:0] 031lowe b /n o 1 72 high e b /n o car_lambda_sel l og 2 t b 2 16 () log 2 = 17.7-6 2 16 } 10 0xa == { = fast_sweeprate 32 * 21.6 (ms/s) = 691.2 (ms/s) = car_swr 2 37 fast_sweeprate t fs 16 ------------------------------------------------------------------ 2 = L64724tm_300.book page 16 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: high data rates b-17 equation b.18 set group 4, apr 33 to 0x2b and apr 32 to 0x8e. group 4, apr 34C35 C set to 0x3334. the value for the upper sweep limit, car_uswl[15:0], is set as explained in the following paragraphs. it should be noted that the upper sweep limit is an approximate value but the approximation to the real sweep limit is accurate enough. assume that the upper sweep limit needed is + 5 mhz. the maximum sweep limit achievable is 0.5 x fs. calculate car_uswl[15:0] as shown in equation b.19 and equation b.20 . equation b.19 equation b.20 set group 4 apr 35 to 0x19 and apr 34 to 0x9a. group 4, apr 36C37 C set to 0xcccc. the value for the lower sweep limit, car_lswl[15:0], is set as explained in the following paragraphs. it should be noted that the lower sweep limit is an approximate value but the approximation to the real sweep limit is accurate enough. assume that the lower sweep limit needed is - 5 mhz. calculate car_lswl[15:0] as shown in equation b.21 and equation b.22 . equation b.21 car_swr 2 37 691.2 10 6 1 21.3 10 6 -------------------------- - 50.0 10 6 16 ------------------------------------------------------------------------------- 2 11 150 , == (2b8e) car_uswl 2 37 sweeplimit fs 2 21 ---------------------------------------------- = car_uswl 2 37 510 6 50.0 10 6 2 21 ------------------------------------------ 6554 == (0x199a) car_lswl 2 37 sweeplimit fs 2 21 ---------------------------------------------- = L64724tm_300.book page 17 friday, april 14, 2000 2:17 pm
b-18 L64724 application notes equation b.22 set group 4, apr 37 to 0xe6 and apr 36 to 0x66. group 4, apr 38C40 C set to 0x51eb8. the value for car_lf_init[23:0] is in accordance with equation b.23 . equation b.23 assuming an initial carrier frequency deviation of + .1 mhz is required, the value for car_lf_init[23:0] is given in equation b.24 . equation b.24 set group 4, apr 40 to 0x05, apr 39 to 0x1e, and apr 38 to 0xb8. group 4, apr 41 C set to 0x65. set the bits in the carrier loop control 1 register as shown in ta b l e b . 4 . car_lswl 2 37 5 C 10 6 50.0 10 6 2 21 ------------------------------------------ - 6554 == (0xe666) car_lf_init 2 37 freqdeviation 2 13 fs ----------------------------------------------------- = car_lf_init 2 37 110 6 2 13 50 10 6 ------------------------------------- 335554 == (0x51eb8) L64724tm_300.book page 18 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: high data rates b-19 if the carrier is locked but the constellation is rotated by 45 degrees, reverse the polarity of bit 6 ( car_error_swap ). group 4, apr 42 C set to 0xaa. this register de?nes the loop bandwidths for a particular baud rate. a good approximation to the equivalent noise bandwidth is given in equation b.25 . equation b.25 for a baud rate of 21.3 mbaud we can choose b l = 6.6 krad/s and therefore w n = 10.6 krad/s. the loop equations are calculated as shown in equation b.26 and equation b.27 . equation b.26 table b.4 carrier loop control 1 register bits bits setting acronym meaning d7 0 car_swp_swap not signi?cant when auto sweep is on d6 1 car_error_swap carrier phase error detector output inverted d5 1 car_auto_swp carrier auto sweep on d4 0 reserved C d3 0 reserved C d2 1 car_ped_sel choose ndaml phase error detector d1 0 car_open carrier loop operates normally d0 1 car_sw carrier sweep on b l 0.0003125 baudrate = b l zw n 2 --------- - 1 1 4 z 2 -------- - + ? ?? = t a w n 2 t 2 k tim l tim ---------------------- - 2 p = L64724tm_300.book page 19 friday, april 14, 2000 2:17 pm
b-20 L64724 application notes equation b.27 the damping factor ( z) is chosen as 1.0, and k tim = 0.0388. using these values we get l tim = fs x decimation_ratio/fb = 50e6 x 1/21.3e6 = 2.34. we can now calculate t a and t b as shown in equation b.28 and equation b.29 . equation b.28 equation b.29 clk_mu_sel[3:0] and clk_lambda_sel[3:0] are de?ned in equation b.31 and equation b.32 . equation b.30 equation b.31 program the four lsbs of apr 42 with 0xa and the four msbs of apr 42 with 0xa. note: group 4, apr 43C48, contain sweep parameters that need to be programmed only if clock sweep is required. these parameters have meaning only when the clk_sw bit (bit d0 of group 4, apr 53) is set to a 1. group 4, apr 43C44 C set to 0x0fa0. the value for the clock sweep rate, clk_swr[15:0], is set according to equation b.32 , assuming a clock sweep rate of 1 mhz/s. t b 2 zw n t k tim l tim ---------------------- - = 2 p t a 10.6 10 3 () 2 1 21.3 10 6 -------------------------- - ? ?? 2 0.0388 2.34 ----------------------------------------------------------------------- 310 6 C == t b 2 10.6 10 3 1 21.3 10 6 -------------------------- - 0.0388 2.34 ---------------------------------------------------------------------- - 11 10 3 C == car_mu_sel l og 2 t a 2 28 () log 2 3 e -6 2 28 ( = () 10 = 0xa = = car_lambda_sel l og 2 t b 2 16 () log 2 = 11 e -3 2 16 } 10 0xa == { = L64724tm_300.book page 20 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: high data rates b-21 equation b.32 set group 4 apr 44 to 0x0f and apr 43 to 0xa0. group 4, apr 45C46 C set to 0x0600. the value for the upper sweep limit, clk_uswl[15:0], is set as explained in the following paragraphs. it should be noted that the upper sweep limit is an approximate value but the approximation to the real sweep limit is accurate enough. assume that the upper sweep limit needed is +10 khz. clk_uswl[15:0] is calculated as shown in equation b.33 . equation b.33 set group 4, apr 46 to 0x06 and apr 45 to 0x00. group 4, apr 47C48 C set to 0xfa00. the value for the lower clock sweep limit, clk_lswl[15:0], is set as explained in the following paragraphs. it should be noted that the lower sweep limit is an approximate value, but the approximation to the real sweep limit is accurate enough. assume that the lower sweep limit needed is - 10 khz. the clk_lswl[15:0] value is calculated as shown in equation b.34 . equation b.34 clk_swr 2 45 sweeprate t fs 1 df_ratio ------------------------ - 16 -------------------------------------------------------- - 2 = clk_swr 2 45 110 6 1 21.3 10 6 -------------------------- - 2 50.0 10 6 116 ----------------------------------------------------------------------------- 4000 == (0xfa0) clk_uswl 2 45 sweeplimit fs 1 df_ratio ----------------------------- 2 22 ---------------------------------------------------------- - 2 = clk_uswl 2 45 10 10 3 50.0 10 6 12 22 ------------------------------------------------------- 1536 == (0x0600) clk_lswl 2 45 10 C 10 3 50.0 10 6 12 22 ------------------------------------------------------- 2 1536 C == (0xfa00) L64724tm_300.book page 21 friday, april 14, 2000 2:17 pm
b-22 L64724 application notes set group 4, apr 48 to 0xfa and apr 47 to 0x00. group 4, apr 49C52 C set to 0x12c78301. choose clk_bias[30:0] according to equation b.35 . equation b.35 fs = sampling frequency at the a/d and fb is the baud rate. set group 4, apr 52 to 0x12, apr 51 to 0xc7, apr 50 to 83, and apr 49 to 01. group 4, apr 53 C set to 0x38. set the bits in the clock loop con?guration register (apr 53) as shown in ta b l e b . 5 . table b.5 clock loop con?guration register bits bits setting acronym meaning d7 0 clk_swp_swap not signi?cant when auto sweep is on or when sweep is off d6 0 clk_error_swap timing error detector output not inverted d5 1 clk_auto_swp automatic internal sweep control d4 1 reserved ser this bit to 1 d3 1 agc_clk_sel integrate over all samples d2 0 reserved clear this bit to 0 d1 0 clk_open enable the clock loop d0 0 clk_sw clock sweep off clk_bias fs 1 df_ratio ----------------------------- 2 28 2 fb ---------------------------------------------------------- - = clk_bias 50.0 10 6 1 2 28 2 21.3 10 6 --------------------------------------------------- - 315065089 == (0x12c7.8301) L64724tm_300.book page 22 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: high data rates b-23 group 4, apr 54 C set to 0x00. set the bits in the demodulator con?guration register (apr 54) as shown in ta b l e b . 6 . group 4, apr 55 C set to 0x00. set the bits in the external output control bits and reset register (apr 55) as shown in ta b l e b . 7 . group 4, apr 56C57 - set to 0x00. group 4, apr 58 C set to 0x14. table b.6 demodulator con?guration register bits bits setting acronym meaning d7 0 snr_est enable snr estimator d6 0 pwrp_tri pwrp not 3-stated d5 0 adc_pd a/d normal operation d4 0 fp_lock_len normal (long) window for phase lock d3 0 pwrp pwrp pin in normal mode d2 to d1 0b00 reserved clear these bits to 0 for normal mode d0 0 clk_alpha_sel alpha value = 0.43 table b.7 external output control bits and reset register bits bits setting acronym meaning d7 0 adc_bp enable adcs d6 0 ob_2c input is offset-binary format d5 to d2 0b0000 xctr[3:0] corresponding output pin = vss d1 0 demod_rst no reset for demodulator d0 0 fec_rst no reset for fec L64724tm_300.book page 23 friday, april 14, 2000 2:17 pm
b-24 L64724 application notes group 4, apr 59C61 C these registers are used to communicate on a serial bus to the tuner using the xctr[3:0] output pins. refer to appendix c for details on programming the spi interface. group 4, apr 62 C set to user preference. set the bits in the group 4, apr 62 register as shown in the following table. group 4, apr 63 C set to 0x63. clear the fmode bit (d7) to 0. set the spi_clk_and bit (d6) to 1 to and the spi byte clock and the dvalidout signal. clear the spi_mode_a_b bit to 0 for mode a. set the spi_n[3:0] bits to 0x03 because the viterbi code rate is 3/4. group 4, apr 64C65 C set to 0x3200. set the spi_gain[9:0] to 50 (0x32) because the oversampling ratio (or) is between 2 and 4. bits setting acronym meaning d7 C serial_b see appendix c, programming the serializer , for more details. d6 to d5 C serial_c[1:0] see appendix c, programming the serializer , for more details. d4 to d1 0b0100 spi_m[3:0] denominator of viterbi code rate = 4 (rate = 3/4) d0 C serial_a see appendix c, programming the serializer , for more details. L64724tm_300.book page 24 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: high data rates b-25 . group 4, apr 66C68 C set to 0x51cac0. set the spi_bias[22:0] value as shown in equation b.36 . equation b.36 in the equation, vcr = 3/4 and or = 50e6/21.3e6. the result is that spibias = 5,360,320 (0x51.cac0.) set group 4, apr 68 to 0x51, apr 67 to 0xca, and apr 66 to 0xc0. group 4, apr 69 C set to 0x4b. set the timing lock threshold (clk_lc_thsl[7:0]) value at 75 (0x4b.) ta b l e b . 8 gives the register values calculated for high data rates. or spi gain 2 to 4 50.0 4 to 8 35.0 8 to 16 15.0 greater than 16 less than 10 spibias 2 24 vcr or -------------------------- = L64724tm_300.book page 25 friday, april 14, 2000 2:17 pm
b-26 L64724 application notes table b.8 high data rate register values apr [5:0] d7 d6 d5 d4 d3 d2 d1 do hex 0 set to 1 re- served pll_n[5:0] 81 1 reserved pll_s[5:0] 14 2 imq dvb_ dss qb pll_t[4:0] 6 3 viterbi code rate[2:0] tei sync2 _ mod sync1 over- ride pll_m[1:0] 18 4 viterbi max data bit count, vmdc1[7:0] 40 5 viterbi max data bit count 2, vmdc2[7:0], low byte 00 6 viterbi max data bit count 2, vmdc2[15:8], middle byte 00 7 viterbi max data bit count 2, vmdc2[23:16], high byte 0f 8 viterbi maximum bit error count[7:0], rate 1/2 1e 9 viterbi maximum bit error count[7:0], rate 2/3 00 10 viterbi maximum bit error count[7:0], rate 3/4 00 11 viterbi maximum bit error count[7:0], rate 5/6 00 12 viterbi maximum bit error count[7:0], rate 6/7 00 13 viterbi maximum bit error count[7:0], rate 7/8 00 14 synchronization word[7:0] 47 15 ber auto rate reserved imq_ en di_ bypass l[1:0] 00 16 reserved sync status select, sss[1:0] sync states acq, ssa [1:0] sync states track, sst[1:0] 00 17 reserved of output selector, os[4:0] 00 18 pll_reset 00 (sheet 1 of 4) L64724tm_300.book page 26 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: high data rates b-27 19 df_select[2:0] df_gain[1:0] df_ratio[2:0] 84 20 reserved pd reserved mf_20_ 35 01 21 pclk_ inv pll_bp lclk_ off clk_div1[4:0] 00 22 clk_div2[7:0] 00 23 dc_offset_on_off [1:0] re- served clk_div2[12:8] c0 24 pwr_ref[7:0] 54 25 reserved int_dc pwr_bw[1:0] 00 26 scale factor for demi, demq, scale[7:0] ba 27 snr estimator threshold, snr_ths[7:0] 64 28 carrier loop lambda, car_lambda_sel[3:0] carrier loop mu, car_mu_sel[3:0] aa 29 carrier phase lock detector threshold, car_lc_thsl[7:0] 1f 30 reserved 00 31 rs bit/byte select errorout_ invert spi_on_ off reserved = 0 20 32 carrier sweep rate, car_swr[7:0] 8e 33 carrier sweep rate, car_swr[15:8] 2b 34 carrier upper sweep limit, car_uswl[7:0] 9a 35 carrier upper sweep limit, car_uswl[15:8] 19 36 carrier lower sweep limit, car_lswl[7:0] 66 37 carrier lower sweep limit, car_lswl[15:8] e6 38 carrier loop filter initialization, car_lf_init[7:0] b8 39 carrier loop filter initialization, car_lf_init[15:8] 1e table b.8 high data rate register values (cont.) apr [5:0] d7 d6 d5 d4 d3 d2 d1 do hex (sheet 2 of 4) L64724tm_300.book page 27 friday, april 14, 2000 2:17 pm
b-28 L64724 application notes 40 carrier loop filter initialization, car_lf_init[23:16] 05 41 car_ swp_ swap car_ error_ swap car_ auto_ swp reserved car_ ped_ sel car_ open car_ sw 65 42 clock loop lambda, clk_lambda_sel[3:0] clock loop mu, clk_mu_sel[3:0] aa 43 clock sweep rate, clk_swr[7:0] a0 44 clock sweep rate, clk_swr[15:8] 0f 45 clock upper sweep limit, clk_uswl[7:0] 00 46 clock upper sweep limit, clk_uswl[15:8] 06 47 clock lower sweep limit, clk_lswl[7:0] 00 48 clock lower sweep limit, clk_lswl[15:8] fa 49 clock loop bias, clk_bias[7:0]] 01 50 clock loop bias, clk_bias[15:8] 83 51 clock loop bias, clk_bias[23:16] c7 52 reserved clock loop bias, clk_bias[30:24] 12 53 clk_ swp_ swap clk_ error_ swap clk_ auto_ swp re- served agc_ clk_ sel re- served clk_ open clk_ sw 38 54 snr_est pwrp_ tri adc_pd fp_ lock_ len pwrp reserved clk_ alpha_ sel 00 55 adc_bps ob_2c external control output bits, xctr[3:0] demod _rst fec_ rst 00 56 reserved 00 57 reserved 00 58 reserved 14 table b.8 high data rate register values (cont.) apr [5:0] d7 d6 d5 d4 d3 d2 d1 do hex (sheet 3 of 4) L64724tm_300.book page 28 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: high data rates b-29 59 serial transmission start data, txsd[6:0] re- served 10 60 serial transmission data, stxd[7:0] 00 61 serial transmission end data, txed[7:0] 00 62 serial_b serial_c[1:0] spi_m[3:0] serial_a 63 fmode spi_clk _and spi_ mode_a _b re- served spi_n[3:0] 63 64 spi_gain[7:0](lsb) 32 65 reserved spi_gain[9:8] 00 66 spi_bias[7:0](lsb) c0 67 spi_bias[15:8](msb) ca 68 reserved spi_bias[22:16] 51 69 timing lock threshold, clk_lc_thsl[7:0] 4b table b.8 high data rate register values (cont.) apr [5:0] d7 d6 d5 d4 d3 d2 d1 do hex (sheet 4 of 4) L64724tm_300.book page 29 friday, april 14, 2000 2:17 pm
b-30 L64724 application notes b.4 qpsk demodulator and fec con?guration example: low data rates this section contains an example of how to con?gure the qpsk demodulator section of the L64724 through its microcontroller interface. this example con?guration is optimized for ?xed rate operation with the following parameters: the registers for this example are con?gured as shown in the following subsections. see table b.14 ,on page b-45 , for a summary of the register settings. group 4, apr 0 C set to 0x81. set bit d7 to 1 and clear bit d6 to 0. based on section 4.2, set the pll_n[5:0] ?eld to 0x01 (pclk = 60 mhz.) group 4, apr 1 C set to 0x04. clear bits d7 and d6 to 0. based on section 4.2, set the pll_s[5:0] bits to 0x04 (pclk = 60 mhz.) group 4, apr 2 C set to 0x01. set the imq bit (d7) to either 1 or 0, clear the dvb_dss bit (d6) bit to 0 for dvb, and clear the qb bit (d5) to 0 for qpsk. based on table 4.2, set the pll_t[4:0] bits to 0x01. transmission rate: 4.0 mbit/s (2.0 mbaud) adc sampling frequency 60 mhz xtal osc 15.00 mhz adc input: 1.0 v p-to-p dc offset control used viterbi rate 1/2 e b /n o 4.0 db model dvb L64724tm_300.book page 30 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: low data rates b-31 group 4, apr 3 C set to 0x09. clear the vcr[2:0] bits (d7 to d5) to 0x00 for rate 1/2, the tei bit (d4) to 0 or 1, set the sync2_mod bit (d3) to 1, clear bit d2 to 0, and based on section 4.2, set the pll_m[1:0] bits to 0x01. group 4, apr 4 C set to 0x40. since the viterbi code rate is 1/2, based on the graph shown in figure 6.4 for an e b /n o = 4.0 (e s /sigma^2 = 7.0,) a choice of 0.24 for vmbec/vmdc1 establishes a valid decision threshold over the entire snr range. equation b.37 shows the relationship between vmbec and vmdc1. equation b.37 choosing vmdc1[7:0] = 64 (0x40) yields a value of 30 (0x1e) for vmbec[7:0]. group 4, apr 5C7 C set to 0x0f0000. the vmdc2[23:0] bits select a second window. the vmdc2[23:0] bits control the window size over which viterbi errors are counted and are used for calculating the ber, not for the auto-synchronization that is controlled by vmdc1. in this example, choose a window size of 3.932 x 10 6 bits = vmdc2[23:0] x 4. other values may work as well. set group 4, apr 7 to 0x0f, apr 6 to 0x00, and apr 5 to 0x00. 0.24 128 vmbec 32 + 256 vmdc 1 ---------------------------------------------- = L64724tm_300.book page 31 friday, april 14, 2000 2:17 pm
b-32 L64724 application notes group 4, apr 8 C set to 0x1e. equation b.37 yields a value for vmbec[7:0] of 30 or 0x1e. group 4, apr 9C13 C set all these registers to 0x00. group 4, apr 14 C set to 0x47. the dvb synchronization word[7:0] value is 0x47. group 4, apr 15 C set to 0x10. clear d7 to 0, clear the auto rate bit (d6) to 0 to obtain the code rate from the vcr, clear the d5 and d4 bits to 0, clear the imq_en bit (d3) to 0 for imq to be determined by apr 2 bit 7, clear the di_bypass bit (d2) to 0 to enable the deinterleaver, and clear the l[1:0] bits (d1, d0) to 0x00 to select zero mismatching bits. group 4, apr 16 C set to 0x00. clear d7 and d6 to 0, clear the sss[1:0] bits (d5 and d4) to 0 to select viterbi decoder sync, clear the ssa[1:0] bits d3 and d2 to 0x00 to set the number of sync words to acquire to three, and clear the sst[1:0] bits (d1 and d0) to 0 to set the number of missed sync words to loss of lock at two. group 4, apr 17 C set to 0x00. clear the d7 and d6 bits to 0, clear the of bit (d5) to 0 for serial channel output mode, and clear the os[4:0] bits (d4 to d0) to 0 to observe the descrambler output. group 4, apr 18 C set to 0x00. write any value to this register to reset the pll module. group 4, apr 19 C set to 0x7a. select the register bits according to the following table. L64724tm_300.book page 32 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: low data rates b-33 see section 5.4, decimation filters, page 5-4 , for more details. group 4, apr 20 C set to 0x11. clear the d7 through d5 bits to 0, clear the pd bit (d4) to 0 for normal operation, clear the d5 through d1 bits to 0, and set the mf_20_35 bit (d0) to 1 for a matched ?lter roll-off factor of 0.35. group 4, apr 21 C set to 0x00. clear the pclk_inv bit (d7) to 0 for a noninverted pclk output. clear the pll_bp bit (d6) to 0 to enable the internal pll to generate the a/d clock. clear the lclk_off bit (d5) to 0 to turn off the lclk signal. clear the clk_div1[4:0] bits (d4 to d0) to 0 because the internal pll is used. group 4, apr 22 C set to 0x00. set apr register 22 to 0x00, because the clk_div2[7:0] bits are unused when the internal pll has been selected. group 4, apr 23 C set to 0xc0. set the dc_offset_on_off[1] bit (d7) to 1 to cause the dc offset compensation after the adc to be activated. set the dc_offset_on_off[0] bit (d6) to 1 to cause the noise feedback to the compensation circuit to be selected. clear the d5 bit to 0. clear the clk_div2[12:8] bits (d4 to d0) to 0, because the clk_div2[12:8] bits are unused when the internal pll has been selected. bits setting parameter meaning d7 to d5 0b011 df_select[2:0] select ?lter 4 (16-band ?lter) d4 to d3 0b11 df_gain[1:0] df_gain = 8 d2 to d0 0b010 df_ratio[2:0] select decimation ratio = 8. L64724tm_300.book page 33 friday, april 14, 2000 2:17 pm
b-34 L64724 application notes group 4, apr 24 C set to 0x54. set the pwr_ref[7:0] bits to 0x54. see section 5.8.1, adc range and power reference, page 5-20 , for more details. group 4, apr 25 C set to 0x03. clear the d7 through d3 bits to 0, clear the int_dc bit (d2) to 0 to disable internal dc offset compensation, and set the pwr_bw[1:0] bits to 0b11 according to section 5.8.2. group 4, apr 26 C set to 0xba. equation b.38 used to calculate the value of scale[7:0]. equation b.38 group 4, apr 27 C set to 0x64. this register is set to a signal-to-noise threshold value dependent on the value of the pwr_ref[7:0] value. the snr_ths[7:0] bits contain a threshold value that indicates a good or bad signal-to-noise ratio. set the snr_ths[7:0] value to 100 (0x64.) group 4, apr 28 C set to 0x58. this register de?nes the loop bandwidths for a particular baud rate. a good approximation to the equivalent noise bandwidth is given in equation b.39 (for low data rates.) equation b.39 for a baud rate of 2.0 mbaud we can choose b l = 15.625 krad/s and therefore w n = 25 krad/s. scale 2047 1 e s n o ------- ? ?? 1 C + 2 pwr_ref -------------------------------------------------- = scale 2047 1 2.51 () 1 C + 284 ----------------------------------------------------- 186 == (0xba) b l 0.003125 baudrate = b l zw n 2 --------- - 1 1 4 z 2 -------- - + ? ?? = L64724tm_300.book page 34 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: low data rates b-35 the loop equations are calculated as shown in equation b.40 and equation b.41 . equation b.40 equation b.41 the damping factor ( z) is chosen as 1.0. k dcar =k digital x 0.78/32.0. k digital is chosen from table 5.4 ,on page 5-19 . for a snr of 4db, k digital = 10, with the result that k dcar = 0.24. using these values, we get l car = fs/fb = 60e6/2.0e6 = 30. we can now calculate t a and t b as shown in equation b.42 and equation b.43 . equation b.42 equation b.43 car_mu_sel[3:0] and car_lambda_sel[3:0] are de?ned as shown in equation b.45 and equation b.46 . equation b.44 equation b.45 program the four lsbs of apr 28 with 0x5 and the four msbs of apr 28 with 0x8. t a w n 2 t 2 k dcar l car --------------------------- = t b 2 zw n t k dcar l car --------------------------- = t a 25 10 3 () 2 1 2.0 10 6 ----------------------- - ? ?? 2 0.24 30 -------------------------------------------------------------- - 1.24 10 6 C == t b 2 () 25 10 3 1 2.0 10 6 ----------------------- - 0.24 30 ------------------------------------------------------------------- 3.4 10 3 C == car_mu_sel l og 2 t a 2 25 () log 2 1.24 e -6 2 25 ( = () 5 = 0x5 = = car_lambda_sel l og 2 t b 2 16 () log 2 = 3.4 e -3 2 16 } 80x8 == { = L64724tm_300.book page 35 friday, april 14, 2000 2:17 pm
b-36 L64724 application notes group 4, apr 29 C set to 0x1f. the recommended value for car_lc_thsl[7:0] is 31 (0x1f) when fp_lock_len (group 4, apr 54) is set to 0. otherwise, set it according to the following table: group 4, apr 30 C set to 0x00. group 4, apr 31 C set to 0x20. set the rs bit/byte select bit (d7) as needed to select the reed- solomon bit or byte error count for group 3 apr 0 and 1. set the errorout_invert bit (d6) as needed to control the polarity of the erroroutn signal. set the spi_on_off bit (d5) to 1. clear bits d4 through d0 to 0. group 4, apr 32C33 C set to 0x11c. the value for the sweep rate, car_swr[15:0], is set according to equation b.46 and equation b.47 . assume a sweep rate of 2 mhz/s is required. equation b.46 equation b.47 set group 4, apr 33 to 0x01 and apr 32 to 0x1c. fp_lock_len car_lc_thsl[7:0] 031lowe b /n o 1 72 high e b /n o car_swr 2 37 sweeprate t fs 16 -------------------------------------------------------- - 2 = (0x11c) car_swr 2 37 210 6 1 2.0 10 6 ----------------------- - 60 10 6 16 ---------------------------------------------------------------- 2 284 == L64724tm_300.book page 36 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: low data rates b-37 group 4, apr 34C35 C set to 0x1110. the value for the upper sweep limit, car_uswl[15:0], is set as explained in the following paragraphs. it should be noted that the upper sweep limit is an approximate value but the approximation to the real sweep limit is accurate enough. assume that the upper sweep limit needed is + 2 mhz. calculate car_uswl[15:0] as shown in equation b.48 and equation b.49 . equation b.48 equation b.49 set group 4, apr 35 to 0x08 and apr 34 to 0x88. group 4, apr 36C37 C set to 0xeefd. the value for the lower sweep limit, car_lswl[15:0], is set as explained in the following paragraphs. it should be noted that the lower sweep limit is an approximate value but the approximation to the real sweep limit is accurate enough. assume that the lower sweep limit needed is - 2 mhz. calculate car_lswl[15:0] as shown in equation b.50 and equation b.51 . equation b.50 equation b.51 set group 4, apr 37 to0xf7 and apr 36 to 0x78. car_uswl 2 37 sweeplimit fs 2 21 ---------------------------------------------- = car_uswl 2 37 210 6 60 10 6 12 21 ---------------------------------------------- - 2184 == (0x0888) car_lswl 2 37 sweeplimit fs 2 21 ---------------------------------------------- = (0xf778) car_lswl 2 37 2 C 10 6 60 10 6 12 21 ---------------------------------------------- - 2184 C == L64724tm_300.book page 37 friday, april 14, 2000 2:17 pm
b-38 L64724 application notes group 4, apr 38C40 C set to 0x006d39. the value for car_lf_init[23:0] is in accordance with equation b.52 . equation b.52 assuming an initial carrier frequency deviation of + .1 mhz is required, the value for car_lf_init[23:0] is given as shown in equation b.53 . equation b.53 set group 4, apr 40 to 0x00, apr 39 to 0x6d, and apr 38 to 0x39. group 4, apr 41 C set to 0x65. set the bits in the carrier loop con?guration register as shown in ta b l e b . 9 . if the carrier is locked but the constellation is rotated by 45 degrees, reverse the polarity of bit 6 ( car_error_swap ). table b.9 carrier loop con?guration register bits bits setting acronym meaning d7 0 car_swp_swap not signi?cant when auto sweep is on d6 1 car_error_swap carrier phase error detector output inverted d5 1 car_auto_swp carrier auto sweep on d4 0 reserved C d3 0 reserved C d2 1 car_ped_sel choose ndaml phase error detector d1 0 car_open carrier loop operates normally d0 1 car_sw carrier sweep on car_lf_init 2 37 freqdeviation 2 13 fs ----------------------------------------------------- = (0x6d39) car_lf_init 2 37 0.1 10 6 2 13 60 10 6 -------------------------------------- - 27961 == L64724tm_300.book page 38 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: low data rates b-39 group 4, apr 42 C set to 0x99. this register de?nes the loop bandwidths for a particular baud rate. a good approximation to the equivalent noise bandwidth is given in equa- tion b.54 . equation b.54 for a baud rate of 21.3 mbaud we can choose b l = .625 krad/s and therefore w n = 1 krad/s. the loop equations are calculated as shown in equation b.55 and equation b.56 . equation b.55 equation b.56 the damping factor ( z) is chosen as 1.0, and k tim = 0.0388. using these values we get l tim = fs x decimation_ratio/fb = 60e6 *(0.25)/2.0e6 = 3.75. we can now calculate t a and t b as shown in equation b.57 and equation b.58 . equation b.57 equation b.58 b l 0.0003125 baudrate = b l zw n 2 --------- - 1 1 4 z 2 -------- - + ? ?? = t a w n 2 t 2 k tim l tim ---------------------- - = t b 2 zw n t k tim l tim ---------------------- - = t a 110 3 () 2 1 2.0 10 6 ----------------------- - ? ?? 2 0.0388 3.75 ----------------------------------------------------------- 0.171 10 5 C == t b 2110 3 1 2.0 10 6 ----------------------- - 0.0388 3.75 ---------------------------------------------------------- - 68.6 10 4 C == L64724tm_300.book page 39 friday, april 14, 2000 2:17 pm
b-40 L64724 application notes clk_mu_sel[3:0] and clk_lambda_sel[3:0] are de?ned as shown in equation b.59 and equation b.60 . equation b.59 equation b.60 program the four lsbs of apr 42 with 0x9 and the four msbs of apr 42 with 0x9. note: group 4, apr 43C48, contain sweep parameters that need to be programmed only if clock sweep is required. these parameters have meaning only when the clk_sw bit (bit d0 of group 4, apr 53) is set to a 1. group 4, apr 43C44 C set to 0x28cc. the value for the clock sweep rate, clk_swr[15:0], is set according to equation b.61 , assuming a clock sweep rate of 10 khz/s. equation b.61 set group 4, apr 44 to 0x28 and apr 43 to 0xcc. group 4, apr 45C46 C set to 0x0940. the value for the upper sweep limit, clk_uswl[15:0], is set as explained in the following paragraphs. it should be noted that the upper sweep limit is an approximate value but the approximation to the real sweep limit is accurate enough. assume that the upper sweep limit needed is + 10 khz. clk_uswl[15:0] is calculated as shown in equation b.62 . car_mu_sel l og 2 t a 2 28 ) log 2 0.171 e -5 2 28 ( = () 9 = 0x9 = = car_lambda_sel l og 2 t b 2 16 () log 2 = 68.6 ( e -4 2 16 ) 90x9 == = (0x28cc) clk_swr 2 45 sweeprate t fs 1 df_ratio ----------------------------- 16 -------------------------------------------------------- - 2 = clk_swr 2 45 10 10 3 1 2.0 10 6 ----------------------- - 60 10 6 0.125 16 ------------------------------------------------------------------- - 2 10444 == L64724tm_300.book page 40 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: low data rates b-41 equation b.62 set group 4, apr 46 to 0x09 and apr 45 to 0x40. group 4, apr 47C48 C set to 0xfbc0. the value for the lower clock sweep limit, clk_lswl[15:0], is set as explained in the following paragraphs. it should be noted that the lower sweep limit is an approximate value, but the approximation to the real sweep limit is accurate enough. assume that the lower sweep limit needed is - 10 khz. the clk_lswl[15:0] value is calculated as shown in equation b.63 . equation b.63 set group 4, apr 48 to 0xfb and apr 47 to 0xc0. group 4, apr 49 - 52 C set to 0x1e000000. choose clk_bias[30:0] according to equation b.64 . equation b.64 fs = sampling frequency at the a/d and fb is the baud rate. set group 4, apr 52 to 0x1e, apr 51 to 0x00, apr 50 to 00, and apr 49 to 00. clk_uswl 2 45 sweeplimit fs 1 df_ratio ----------------------------- 2 22 ---------------------------------------------------------- - 2 = (0x0940) clk_uswl 2 45 10 10 3 60 10 6 0.125 2 22 ---------------------------------------------------------- 2 2368 10 == (0xfbc0) clk_lswl 2 45 10 C 10 3 60 10 6 0.125 2 22 ---------------------------------------------------------- 2 2368 10 C == clk_bias fs 1 df_ratio ----------------------------- 2 28 2 fb ---------------------------------------------------------- - = (0x1e00.0000) clk_bias 60 10 6 0.125 2 28 2 2.0 10 6 ---------------------------------------------------------- 503316480 == L64724tm_300.book page 41 friday, april 14, 2000 2:17 pm
b-42 L64724 application notes group 4, apr 53 C set to 0x38 . set the bits in the clock loop con?guration register (apr 53) as shown in table b.10 . group 4, apr 54 C set to 0x00. set the bits in the demodulator con?guration register (apr 54) as shown in table b.11 . table b.10 clock loop con?guration register bits bits setting acronym meaning d7 0 clk_swp_swap not signi?cant when auto sweep is on or when sweep is off d6 0 clk_error_swap timing error detector output not inverted d5 1 clk_auto_swp automatic internal sweep control d4 1 reserved set this bit to 1 d3 1 agc_clk_sel integrate over all samples d2 0 reserved clear this bit to 0 d1 0 clk_open enable the clock loop d0 0 clk_sw clock sweep off L64724tm_300.book page 42 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: low data rates b-43 group 4, apr 55 C set to 0x00. set the bits in the external output control bits and reset register (apr 55) as shown in table b.12 . group 4, apr 56 - 57 - set to 0x00. group 4, apr 58 - set to 0x14. group 4, apr 59C61 C these registers are used to communicate on a serial bus to the tuner using the xctr[3:0] output pins. refer to appendix c for details on programming the spi interface. group 4, apr 62 C set according to user preference. table b.11 demodulator con?guration register bits bits setting acronym meaning d7 0 snr_est enable snr estimator d6 0 pwrp_tri pwrp not 3-stated d5 0 adc_pd a/d normal operation d4 0 fp_lock_len normal (long) window for phase lock d3 0 pwrp pwrp pin in normal mode d2 to d1 0b00 reserved clear these bits to 0 for normal mode d0 0 clk_alpha_sel alpha value = 0.43 table b.12 external output control bits and reset register bits bits setting acronym meaning d7 0 adc_bp enable adcs d6 0 ob_2c input is offset-binary format d5 to d2 0b0000 xctr[3:0] corresponding output pin = vss d1 0 demod_rst no reset for demodulator d0 0 fec_rst no reset for fec L64724tm_300.book page 43 friday, april 14, 2000 2:17 pm
b-44 L64724 application notes set the bits in the group 4, apr 62 register as shown in table b.13 . group 4, apr 63 C set to 0x63. clear the fmode bit (d7) to 0. set the spi_clk_and bit (d6) to 1 to and the spi byte clock and the data valid signal. set spi_mode_a_b to 0 for mode a. set spi_n[3:0] to 3 since the viterbi code rate is 3/4. group 4, apr 64 C 65 C set to 0x0008. set the spi_gain[9:0] to 8 because the oversampling ratio (or) is 30. set group 4, apr 65 to 0x08 and apr 64 to 0x00. group 4, apr 66 C 68 C set to 0x066666. set the spi_bias[22:0] value as shown in equation b.65 . equation b.65 table b.13 group 4, apr 62 register bits bits setting acronym meaning d7 C serial_b refer to appendix c, programming the serializer , for more details. d6 to d5 C serial_c[1:0] refer to appendix c, programming the serializer , for more details. d4 to d1 0b0100 spi_m[3:0] denominator of viterbi code rate = 4 (rate = 3/4) d0 C serial_a refer to appendix c, programming the serializer , for more details. or spi gain 2 to 4 50.0 4 to 8 35.0 8 to 16 15.0 greater than 16 less than 10 spibias 2 24 vcr or -------------------------- = L64724tm_300.book page 44 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: low data rates b-45 in the equation, vcr = 3/4 and or = 60e6/2e6, so spibias = 419430 (0x06.6666). set group 4, apr 68 to 0x06, apr 67 to 0x66, and apr 66 to 0x66. group 4, apr 69 C set to 0x4b. set the timing lock threshold (clk_lc_thsl[7:0]) value at 75 (0x4b.) table b.14 gives the register values calculated for low data rates. . table b.14 low data rate register values apr [5:0] d7 d6 d5 d4 d3 d2 d1 do hex 0 set to 1 re- served pll_n[5:0] 81 1 reserved pll_s[5:0] 04 2 imq dvb_ dss qb pll_t[4:0] 01 3 viterbi code rate[2:0] tei sync2 _mod reserved pll_m[1:0] 09 4 viterbi max data bit count, vmdc1[7:0] 40 5 viterbi max data bit count 2, vmdc2[7:0], low byte 00 6 viterbi max data bit count 2, vmdc2[15:8], middle byte 00 7 viterbi max data bit count 2, vmdc2[23:16], high byte 00 8 viterbi maximum bit error count[7:0], rate 1/2 1e 9 viterbi maximum bit error count[7:0], rate 2/3 00 10 viterbi maximum bit error count[7:0], rate 3/4 00 11 viterbi maximum bit error count[7:0], rate 5/6 00 12 viterbi maximum bit error count[7:0], rate 6/7 00 13 viterbi maximum bit error count[7:0], rate 7/8 00 14 synchronization word[7:0] 47 (sheet 1 of 4) L64724tm_300.book page 45 friday, april 14, 2000 2:17 pm
b-46 L64724 application notes 15 reserved auto rate reserved imq_ en di_ bypass l[1:0] 10 16 reserved sync status select, sss[1:0] sync states acq, ssa [1:0] sync states track, sst[1:0] 00 17 reserved of output selector, os[4:0] 00 18 pll_reset 00 19 df_select[2:0] df_gain[1:0] df_ratio[2:0] 7a 20 reserved pd reserved mf_20_ 35 11 21 pclk_ inv pll_bp lclk_ off clk_div1[4:0] 00 22 clk_div2[7:0] 00 23 dc_offset_on_off [1:0] re- served clk_div2[12:8] c0 24 pwr_ref[7:0] 54 25 reserved int_dc pwr_bw[1:0] 03 26 scale factor for demi, demq, scale[7:0] ba 27 snr estimator threshold, snr_ths[7:0] 64 28 carrier loop lambda, car_lambda_sel[3:0] carrier loop mu, car_mu_sel[3:0] 58 29 carrier phase lock detector threshold, car_lc_thsl[7:0] 1f 30 reserved 00 31 rs bit/byte select errorout _ invert spi_on _off reserved 20 32 carrier sweep rate, car_swr[7:0] 1c 33 carrier sweep rate, car_swr[15:8] 88 34 carrier upper sweep limit, car_uswl[7:0] 08 table b.14 low data rate register values (cont.) apr [5:0] d7 d6 d5 d4 d3 d2 d1 do hex (sheet 2 of 4) L64724tm_300.book page 46 friday, april 14, 2000 2:17 pm
qpsk demodulator and fec con?guration example: low data rates b-47 35 carrier upper sweep limit, car_uswl[15:8] 78 36 carrier lower sweep limit, car_lswl[7:0] f7 37 carrier lower sweep limit, car_lswl[15:8] ee 38 carrier loop filter initialization, car_lf_init[7:0] 39 39 carrier loop filter initialization, car_lf_init[15:8] 6d 40 carrier loop filter initialization, car_lf_init[23:16] 00 41 car_ swp_ swap car_ error _swap car_ auto_ swp reserved car_ ped_ sel car_ open car_ sw 65 42 clock loop lambda, clk_lambda_sel[3:0] clock loop mu, clk_mu_sel[3:0] 99 43 clock sweep rate, clk_swr[7:0] cc 44 clock sweep rate, clk_swr[15:8] 28 45 clock upper sweep limit, clk_uswl[7:0] 40 46 clock upper sweep limit, clk_uswl[15:8] 09 47 clock lower sweep limit, clk_lswl[7:0] c0 48 clock lower sweep limit, clk_lswl[15:8] fb 49 clock loop bias, clk_bias[7:0]] 00 50 clock loop bias, clk_bias[15:8] 00 51 clock loop bias, clk_bias[23:16] 00 52 reserved clock loop bias, clk_bias[30:24] 00 53 clk_ swp_ swap clk_ error _swap clk_ auto_ swp set to 1 agc_ clk_ sel reserved clk_ open clk_ sw 38 54 snr_ est pwrp_ tri adc_ pd fp_ lock_ len pwrp reserved clk_ alpha _sel 00 table b.14 low data rate register values (cont.) apr [5:0] d7 d6 d5 d4 d3 d2 d1 do hex (sheet 3 of 4) L64724tm_300.book page 47 friday, april 14, 2000 2:17 pm
b-48 L64724 application notes 55 adc_bp ob_2c external control output bits, xctr[3:0] de- mod_ rst fec_ rst 00 56 reserved 00 57 reserved 00 58 reserved 14 59 serial transmission start data, txsd[6:0] re- served 10 60 serial transmission data, stxd[7:0] 00 61 serial transmission end data, txed[7:0] 00 62 serial_b serial_c[1:0] spi_m[3:0] serial_ a 63 fmode spi_ clk_ and spi_ mode_ a_b re- served spi_n[3:0] 63 64 spi_gain[7:0](lsb) 08 65 reserved spi_gain[9:8] 00 66 spi_bias[7:0](lsb) 66 67 spi_bias[15:8](mb) 66 68 reserved spi_bias[23:16] 06 69 timing lock threshold clk_lc_thsl[7:0] 4b table b.14 low data rate register values (cont.) apr [5:0] d7 d6 d5 d4 d3 d2 d1 do hex (sheet 4 of 4) L64724tm_300.book page 48 friday, april 14, 2000 2:17 pm
L64724 satellite receiver c-1 appendix c programming the serializer this appendix explains how to program the serializer module and shows the signal waveforms corresponding to serializer 2- and 3-wire operation. it contains the following sections: section c.1, serializer overview section c.2, serializer interface signals and con?guration registers section c.3, programming for serial mode (2-wire compliant) section c.4, programming for 3-wire mode this chapter provides complete information on how to use the L64724 registers for serializer operation, but does not provide information on how to program the registers for a speci?c application for the bits, which depends on the addressed slave device. c.1 serializer overview the serializer implements a write-only interface for serial 2- or 3-wire compliant devices. a microprocessor or microcontroller writes to the group 4 address pointer registers (apr) 59C62 to control serializer operation. note: apr 62 needs the applicable bits (serial_a, serial_b, and serial_c) programmed before writing to apr 59C61. in the case of a 2-wire compliant slave, the serializer may be used to perform writes to the slave as follows: write to apr 59 (txsd)generates the start condition write to apr 60 (stxd)generates subsequent data L64724tm_300.book page 1 friday, april 14, 2000 2:17 pm
c-2 programming the serializer write to apr 61(txed)generates the last byte that is to be written, followed by a stop condition the method used to control the serializer frees up the external microprocessor or the on-board microcontroller to perform other critical operations. similarly, the serializer may be used to implement the 3-wire interface in any of the three modes of the 3-wire interface (see section c.4, programming for 3-wire mode, page c-6 .) the pinouts and a detailed description of the operation of the serializer are outlined in the following sections. c.2 serializer interface signals and con?guration registers txsd[6:0] txsd[6:0] provide the 7-bit slave address of the tuner chip and comes from group 4, apr 59, of the microprocessor interface (upi.) bit 7 is the msb of the slave address. the serializer module serializes the slave address and outputs it on xctr_out[1]. txed[7:0] the content of this register is the last data of the serial interface write cycle. it is an 8-bit value stored in group 4, apr 61 of the upi. stxd[7:0] this register holds the data that is serialized and sent out on the serial interface by the serializer. this value comes from group 4, apr 60 of the upi, and is used when the upi or the uc wants to write two or more data bytes to the tuner. xctr[2] (enable) xctr[2] is a bit in the group 4, apr 55 register that controls the enable signal on the xctr_out[2] pin within the 3-wire interface. when the enable signal is high, the data on the data bus is valid. L64724tm_300.book page 2 friday, april 14, 2000 2:17 pm
serializer interface signals and con?guration registers c-3 xctr[1] (sclk) xctr[1] is a bit in the group 4, apr 55 register that controls the sclk signal on the xctr_out[1] pin. sclk operates at a maximum of 394.74 khz and is obtained from a divide by 38 counter operating at the rate of the crystal clock connected to the L64724. if the crystal is at 15 mhz, the sclk signal is at 15 mhz divided by 38 (394.74 khz.) for a 10 mhz crystal, sclk is 263.16 khz. xctr[0] (sdata) xctr[0] is a bit in the group 4, apr 55 register that controls the sdata signal on the xctr_out[0] pin. sdata is the serial data output within the 3-wire interface. serial_a the serial_a bit indicates whether the output pins xctr_out[2:0] are to be controlled directly as programmed in the group 4 register external control output bits, xctr[2:0], or by the serializer module with data from the txsd, stxd, and txed registers. when the bit is 0 (the default), it indicates that control is as dictated by xctr[2:0]. serial_c[1:0] serial transmission control bit c the serial_c[1:0] bits control whether a serial 2-wire or a 3-wire protocol is used to serialize data. the following table outlines the options: serial_c[1:0] selected function 0 0 2-wire serial interface 0 1 3-wire interface, enable high for all valid data 1 0 3-wire interface, enable high for 1 clock cycle at the start of data transfer 1 1 3-wire interface, enable high for 1 clock cycle at the end of data transfer L64724tm_300.book page 3 friday, april 14, 2000 2:17 pm
c-4 programming the serializer c.3 programming for serial mode (2-wire compliant) to set the serializer in a mode to produce 2-wire compliant signals on the sdata (xctr_out[1]) and the sclk (xctr_out[0]) signal lines, the serial_c register (group 4, apr 62[6:5]) must be programmed to 0b00. note: only writes to a 2-wire compliant slave can be accomplished using the serializerit does not perform read operations. furthermore, the serializer assumes that the acknowledge signal is generated properly, every 9th sclk cycle, by the slave that the serializer is addressing. follow the steps outlined below to address the slave and perform subsequent write cycles to it. c.3.1 single data write 1. write txsd (7-bit slave address) 2. wait (11 sclk cycles) 3. write txed (8-bit data) c.3.2 two data writes 1. write txsd (7-bit slave address) 2. wait (11 sclk cycles) 3. write stxd (8-bit data) 4. wait (11 sclk cycles) 5. write txed (8-bit data) c.3.3 multiple-data writes 1. write txsd (7-bit slave address) 2. wait (11 sclk cycles){ 3. for (i =1; i < #data_bytes; i++) write stxd (8-bit data) wait (11 sclk cycles) } write txed (8-bit data) figure c.1 shows the 2-wire serializer operation. L64724tm_300.book page 4 friday, april 14, 2000 2:17 pm
programming for serial mode (2-wire compliant) c-5 figure c.1 2-wire compliant interface apr serial_reg_wr_pulse sclk s data 11 sclk cycles 11 sclk cycles 11 sclk cycles 8-bit data plus ack_b cycle stop condition start condition (xctr_out[1]) (xctr_out[0]) txsd txed txsd stxd txed L64724tm_300.book page 5 friday, april 14, 2000 2:17 pm
c-6 programming the serializer c.4 programming for 3-wire mode to set the serializer in a mode to produce 3-wire interface compliant signals on the sdata (xctr_out[1]), sclk (xctr_out[0]), and the enable (xctr_out[2]) signals, the serial_c register (group 4, apr 62[6:5]) must be programmed as shown in the table below: note: only writes to a 3-wire compliant slave can be accomplished using the serializerit does not perform read operations. follow the steps outlined below, written as pseudo-code, to address the slave and perform subsequent write cycles to it. c.4.1 single data write 1. write txed (8-bit data) c.4.2 two data writes 1. write stxd (8-bit slave-address) 2. wait (11 sclk cycles) 3. write txed (8-bit data) c.4.3 multiple-data writes 1. write stxd (8-bit data) 2. wait (11 sclk cycles){ 3. for (i =1; i < #data_bytes; i++) write stxd(8-bit data) wait (11 sclk cycles) } write txed(8-bit data) figure c.2 shows the 3-wire serializer operation. serial_c[1:0] selected function 0 1 3-wire interface, enable high for all valid data 1 0 3-wire interface, enable high for 1 clock cycle at the start of data transfer 1 1 3-wire interface, enable high for 1 clock cycle at the end of data transfer L64724tm_300.book page 6 friday, april 14, 2000 2:17 pm
programming for 3-wire mode c-7 figure c.2 3-wire interface apr serial_reg_wr_pulse sclk sdata 11 sclk cycles 11 sclk cycles 11 sclk cycles (xctr_out[0]) (xctr_out[1]) txd txed stxd stxd txed enable xctr_out[2] L64724tm_300.book page 7 friday, april 14, 2000 2:17 pm
c-8 programming the serializer c.4.4 example - write 28 bits of data using the 3-wire mode. data writes using the 3-wire interface are possible with a granularity of eight bits. to write data that is not divisible by eight, some padding of dummy data is necessary. for instance, if a 28-bit message is to be sent to the tuner, four 8-bit data bytes should be sent with the ?rst high nibble (4 bits) being the dummy bits, followed by the 4 bits that are to be sent to the tuner. an illustration is shown below. figure c.3 28-bit write using 3-wire mode dummy bits 28-bits to the tuner msb msb msb msb L64724tm_300.book page 8 friday, april 14, 2000 2:17 pm
L64724 satellite receiver d-1 appendix d a/d converters this appendix discusses the analog-to-digital converters (adcs) used in the L64724. the adcs sample the signal from the i/q downconverters at the appropriate oversampling rate and output a 6-bit sign-magnitude equivalent digital signal. this chapter contains the following sections: section d.1, adc overview section d.2, board level interface section d.3, dc characteristics section d.4, ac characteristics L64724tm_300.book page 1 friday, april 14, 2000 2:17 pm
d-2 a/d converters d.1 adc overview two 6-bit ?ash adcs generate the digitized data stream at the input of the demodulator. the interconnection of the adcs with other modules and their connections with the L64724 i/o pins are shown in figure d.1 . figure d.1 adc connections for L64724 d.2 board level interface the adcs require some additional circuitry at the board level. figure d.2 shows sample circuitry that connects to the adc-related pins on the L64724. 6-bit adc cp dout[5:0] 6-bit adc cp dout[5:0] adc_bypass demodulator m p interface adcvddq adcvrefq adcvrefqn qbias qvin ibypass[5:0] qbypass[5:0] ri[5:0] rq[5:0] adcvssq adcvddi adcvrefi adcvrefin ibias ivin adcvssi L64724tm_300.book page 2 friday, april 14, 2000 2:17 pm
board level interface d-3 figure d.2 adc board level interface dout[5:0] 6-bit flash adc qbias adcvrefq adcvrefqn adcvddq adcvssq qvin dout[5:0] ibias adcvrefi adcvrefin adcvddi adcvssi ivin 3.3 v tuner output tuner output L64724 10 m h analog ground 0.01 m f 0.01 m f 3.3 m f m5806-md 1.0 m f 1.0 m f 39 kohm 6-bit flash adc satellite receiver memory memory 10 m f 10 m f 3 4 5 6 7 8 9 10 11 12 13 14 internal voltage reference generator no connect 3.3 v 0.1 m f L64724tm_300.book page 3 friday, april 14, 2000 2:17 pm
d-4 a/d converters it is recommended that the ?lter components connected to the adcvddq/adcvssq and adcvddi/addvssi pins be placed in close proximity to their respective pins. d.2.1 analog input impedance the analog input (ivin, qvin) capacitance is speci?ed to be typically 10 pf. no input resistance is speci?ed because the input is connected to the gate of a fet or an array of fets. the dc resistance for the input is very high (millions of ohms), only degraded by leakage current. however, due to the capacitance, the input impedance decreases with increase in input frequency. the source impedance should be kept as low as possible. d.2.2 analog input range the recommended analog input range is from 0 to 1 v. the actual top of the range is set by the voltage at adcvrefi (adcvrefq), which is recommended to be 1 v. the actual bottom of the range is the voltage at adcvrefin (adcvrefqn), which is 0 v, or analog ground. while it is possible to set up the analog input range to be different from the 0 to 1 v range, be aware that if adcvrefi (adcvrefq) is decreased from 1 v, the linearity of the a/d suffers. it is not recommended that the voltage be more than 10% above 1 v. the L64724 internally generates the dc offset for the analog input (ivin, qvin). d.2.3 reference voltage the L64724 internally generates the reference voltage for the dual adcs. d.2.4 external bias current the external bias current is recommended to be 50 m a, which is the bias current for the array of differential pair fet comparators inside the a/d converter. the external resistor sinks the bias current. L64724tm_300.book page 4 friday, april 14, 2000 2:17 pm
dc characteristics d-5 d.3 dc characteristics ta b l e d. 1 shows the dc characteristics for the adc modules. . d.4 ac characteristics ta b l e d. 2 shows the ac characteristics for the adc modules. . table d.1 dc characteristics parameter min typ max units supply voltage (vdd and avdd) 2.97 3.3 3.63 v resolution 6 bits analog input range 0 1 v external bias current C 50 C m a differential nonlinearity C 1/2 C lsb integral nonlinearity C 1/2 C lsb analog input capacitance C 10 C pf ladder resistance (vref to vrefn) 30 70 200 w table d.2 ac characteristics parameter min typ max units clock rate C C 90 mhz supply current (from avdd) C C 90 ma supply current (from vdd) C C 4 ma L64724tm_300.book page 5 friday, april 14, 2000 2:17 pm
d-6 a/d converters L64724tm_300.book page 6 friday, april 14, 2000 2:17 pm
L64724 satellite receiver e-1 appendix e L64724 on-chip microcontroller this appendix describes the l64274 on-chip microcontroller and contains the following sections: section e.1, L64724 microcontroller instruction set, page e-2 section e.2, microcontroller address map, page e-5 the features of the L64724 on-chip microcontroller are as follows: a 24-bit accumulator 12-bit instructions, with a 4-bit opcode and 8-bit data?eld code size of 256 instructions memory size of 256 registers (8-bits each) figure e.1 shows how the L64724 uc and the host microprocessor access the L64724 con?guration and status registers. for more details on L64724 registers, refer to chapter 3, L64724 registers. L64724tm_300.book page 1 friday, april 14, 2000 2:17 pm
e-2 L64724 on-chip microcontroller figure e.1 registers shared between the host up and L64724 m c e.1 L64724 microcontroller instruction set table e.1 lists the instructions available in the m c. host m p group 2 interrupt registers group 3 status registers group 4 demod, fec con?guration group 5 m c instructions = 256 x 12 m c con?guration m c m c registers (all 8 bits) virtual to physical mapping 0C31 = scratchpad group 6 ramtest upi registers 12-bit instructions 4-bit opcode 8-bit data?eld 31-255 = upi regs L64724 table e.1 L64724 m c instruction set mnemonic expansion opcode [11:8] data?eld [7:0] description cla clear acc 0000 xxxxxxxx set accumulator value to all zero ldali load acc low immediate 0001 immediate 8-bit data load immediate 8 bit data into accumula- tors low byte (acc[7:0]). other accumulator bytes do not change. ldami load acc middle immediate 0010 immediate 8-bit data load immediate 8 bit data into accumula- tors middle byte (acc[15:8]). other accumulator bytes do not change. (sheet 1 of 3) L64724tm_300.book page 2 friday, april 14, 2000 2:17 pm
L64724 microcontroller instruction set e-3 ldalr load acc low register 0011 8-bit register address load 8 bit register value into accumulators low byte. the registers address is given as immediate data in the commands data ?eld. srbit set/reset bit 0100 axxxxbcd set speci?ed bit in accumulators low byte to given value. a = value (0 or 1). bcd = bit position 000 = acc[0], 001 = acc[1], 010 = acc[2], 011 = acc[3], 100 = acc[4], 101 = acc[5], 110 = acc[6], 111 = acc[7]. addalr add acc low register 0101 8-bit register address add 8-bit unsigned register value to accu- mulators low byte. the added value is positioned opposite acc[7:0], with no sign extension. the registers address is given in the instructions data?eld. addamr add acc middle register 0110 8-bit register address add 8 bit signed register value * 2 8 to accu- mulator[15:0]. the register address is given in the instructions data?eld. the register value is positioned opposite accumulator bits [15:8] after appropriate sign-extension (to 24 bits), and zero-padding. subamr subtract acc middle register 0111 8-bit register address subtract 8 bit signed register value * 2 8 from accumulator. the register address is given in the instructions data?eld. the reg- ister value is positioned opposite accumulator bits [15:8] after appropriate sign-extension to 24 bits, and zero-padding. star store acc register 1000 8-bit register address store accumulators low byte - acc[7:0] in register whose address is given in the instructions data?eld. wtclks wait clock periods 1001 8-bit unsigned wait for speci?ed number of clock periods before loading next instruction. the instruction will take the speci?ed num- ber of clock periods + 2 for execution. table e.1 L64724 m c instruction set (cont.) mnemonic expansion opcode [11:8] data?eld [7:0] description (sheet 2 of 3) L64724tm_300.book page 3 friday, april 14, 2000 2:17 pm
e-4 L64724 on-chip microcontroller asa arithmetic shift acc 1010 xxxxxabc arithmetic shift to accumulator value, according to bits abc in instructions data?eld. a = direction of shift 0 = left shift with zero padding 1 = right shift with sign extension bc = amount of shift 00 = 1-bit shift 01 = 2-bit shift 10 = 4-bit shift 11 = 8-bit shift the sign bit = acc(23) retains its value dur- ing all right and left arithmetic shifts. declp decrement loop control register 1011 xxxxxxab decrement speci?ed scratch pad register dedicated for loop control. 00 = decrement lp0 01 = decrement lp1 10 = decrement lp2 br branch 1100 relative 8-bit instruction address in twos complement branch to the speci?ed uc program line. the relative branching address is given in the instructions data ?eld. jump to relative address + 1. skz skip on zero 1101 abcdefgh skip the next instruction if the result of applying the speci?ed and-or mask on the accumulators low byte results in a logical zero. acc[7:0] = acc[7:0], in other words, its value is not affected by the skz instruction. sknz skip on non-zero 1110 abcdefgh skip the next instruction if the results of applying the speci?ed mask on the accumu- lators low byte results in non-zero. acc[7:0] = acc[7:0], i.e. its value is not affected by the sknz instruction wtsymbs wait valid demod symbols 1111 8-bit unsigned wait until timer count down completed, the timer counts valid demod symbols. formula for number of clk cycles it takes for this instruction is to be included. table e.1 L64724 m c instruction set (cont.) mnemonic expansion opcode [11:8] data?eld [7:0] description (sheet 3 of 3) L64724tm_300.book page 4 friday, april 14, 2000 2:17 pm
microcontroller address map e-5 e.2 microcontroller address map table e.2 shows the m cto m p address mapping. table e.2 microcontroller address map m c_add m p_apr d7 d6 d5 d4 d3 d2 d1 do r/w by m c scratch pad 1 0 n/a loop control register 0, lp0[7:0] r/w 1 loop control register 1, lp1[7:0] 2 loop control register 2, lp2[7:0] 3 loop control register 2 status, lp_status[2:0] 4 accumulator status, acc_status 3 [2:0] 5 scratch pad register 0, sp0[7:0] 6 scratch pad register 1, sp1[7:0] 7 scratch pad register 2, sp2[7:0] 8 scratch pad register 3, sp3[7:0] 9 scratch pad register 4, sp4[7:0] 10 scratch pad register 5, sp5[7:0] 11 scratch pad register 6, sp67:0] 12 scratch pad register 7, sp7[7:0] 13 m c_con?guration, m c_config[7:0] 4 r .. 5 group 2 32 0 group 2 system status register sts[7:0] r 33 1 group 2 system status register sts[15:8] r 34 2 group 2 system status register sts[[23;16] r 35 6 3 group 2 uc interrupt register, uc_i[7:0] r/w .. group 3 64 0 reed-solomon corrected error count low byte, cec[7:0] r 65 1 reed-solomon corrected error count high byte, cec[15:8] 66 2 reed-solomon uncorrected error count low byte, uec[7:0] 67 3 reed-solomon uncorrected error count high byte, uec[15:0] 68 4 viterbi bit error rate count low byte, vberc[7:0] (sheet 1 of 5) L64724tm_300.book page 5 friday, april 14, 2000 2:17 pm
e-6 L64724 on-chip microcontroller group 3 (cont.) 69 5 viterbi bit error rate count high byte, vberc[15:8] r/w 70 6 demod _snr xctr_i n reserved 71 7 nco frequency deviation, car_ncof[7:0] 72 8 nco frequency deviation, car_ncof[15:8] 73 9 nco frequency deviation, car_ncof[23:16] 74 10 agc loop voltage meter, pwr_lvl[7:0] 75 11 s2_fl uc active car_ lcf car_ lc clk_l cf s3 s2 s1 76 12 reserved ri read back, ri[5:0] 77 13 reserved rq read back, rq[5:0] 78 14 reserved viterbi code rate[2:0] 79 15 reed-solomon false lock uncorrected error count low byte, uecfl[7:0] 80 16 reed-solomon false lock uncorrected error count high byte, uecfl[15:0] 81 7 17 uc_status_byte4 [7:0] 82 18 uc_status_byte3 [7:0] 83 19 uc_status_byte2 [7:0] 84 20 uc_status_byte1 [7:0] 85 21 uc_status_byte0 [7:0] 86 22 demod snr estimate, snr[7:0] 87 23 reserved demod snr estimate, snr[11:8] group 4 128 0 en tstn pll_n[5:0] r/w 129 1 iddtn cnt_outl pll_s[5:0] 130 2 imq dvb_ dss qb pll_t[4:0] 131 3 viterbi code rate[2:0] tei sync2 _mod sync1 over ride pll_m[1:0] table e.2 microcontroller address map (cont.) m c_add m p_apr d7 d6 d5 d4 d3 d2 d1 do r/w by m c (sheet 2 of 5) L64724tm_300.book page 6 friday, april 14, 2000 2:17 pm
microcontroller address map e-7 group 4 (cont.) 132 4 viterbi max data bit count, vmdc1[7:0] r/w 133 5 viterbi max data bit count 2, vmdc2[7:0], low byte 134 6 viterbi max data bit count 2, vmdc2[15:8], middle byte 135 7 viterbi max data bit count 2, vmdc2[23:16], high byte 136 8 viterbi maximum bit error count[7:0], rate 1/2 137 9 viterbi maximum bit error count[7:0], rate 2/3 138 10 viterbi maximum bit error count[7:0], rate 3/4 139 11 viterbi maximum bit error count[7:0], rate 5/6 140 12 viterbi maximum bit error count[7:0], rate 6/7 141 13 viterbi maximum bit error count[7:0], rate 7/8 142 14 synchronization word[7:0] 143 15 ber auto rate ber_ nor new_ ber imq_ en di_by pass l[1:0] 144 16 bf sync2 freeze sync status select, sss[1:0] sync states acq, ssa [1:0] sync states track, sst[1:0] 145 17 sync_ step sync2 rst enable of output selector, os[4:0] 146 18 pll_reset 147 19 df_select[2:0] df_gain[1:0] df_ratio[2:0] 148 20 dem_ bp st1_ bp ram test pd mf_ 20_35 149 21 pclk_ inv pll_ bp res. clk_div1[4:0] 150 22 clk_div2[7:0] 151 23 reserved] clk_div2[12:8] 152 24 pwr_ref[7:0] 153 25 reserved int_ dc pwr_bw [1:0] 154 26 scale factor for demi, demq, scale[7:0] 155 27 snr estimator threshold, snr_ths[7:0] 156 28 carrier loop lambda, car_lambda_sel[3:0] carrier loop mu, car_mu_sel[3:0] 157 29 carrier phase lock detector threshold, car_lc_thsl[7:0] table e.2 microcontroller address map (cont.) m c_add m p_apr d7 d6 d5 d4 d3 d2 d1 do r/w by m c (sheet 3 of 5) L64724tm_300.book page 7 friday, april 14, 2000 2:17 pm
e-8 L64724 on-chip microcontroller group 4 (cont.) 158 30 carrier frequency lock detector threshold, car_lcf_thsl[7:0] r/w 159 31 reserved carrier frequency lock detector threshold, car_lcf_thsl[12:8] 160 32 carrier sweep rate, car_swr[7:0] 161 33 carrier sweep rate, car_swr[15:8] 162 34 carrier upper sweep limit, car_uswl[7:0] 163 35 carrier upper sweep limit, car_uswl[15:8] 164 36 carrier lower sweep limit, car_lswl[7:0] 165 37 carrier lower sweep limit, car_lswl[15:8] 166 38 carrier loop filter initialization, car_lf_init[7:0] 167 39 carrier loop filter initialization, car_lf_init[15:8] 168 40 carrier loop filter initialization, car_lf_init[23:16] 169 41 car_ swp_ swap car_ error _swap car_ auto_ swp agc_ input_ sel tim_ jit_?r_ en car_ pe_ sel car_ open car_ sw 170 42 clock loop lambda, clk_lambda_sel[3:0] clock loop mu, clk_mu_sel[3:0] 171 43 clock sweep rate, clk_swr[7:0] 172 44 clock sweep rate, clk_swr[15:8] 173 45 clock upper sweep limit, clk_uswl[7:0] 174 46 clock upper sweep limit, clk_uswl[15:8] 175 47 clock lower sweep limit, clk_lswl[7:0] 176 48 clock lower sweep limit, clk_lswl[15:8] 177 49 clock loop bias, clk_bias[7:0]] 178 50 clock loop bias, clk_bias[15:8] 179 51 clock loop bias, clk_bias[23:16] 180 52 res clock loop bias, clk_bias[30:24] 181 53 clk_ swp_ swap clk_ error _swap clk_ auto_ swp clk_lc_thsl [1:0] clk_ pe_ sel clk_ open clk_ sw 182 54 snr_ est pwrp_ tri adc_ pd fp_ lock _len pwrp f_ lock_ test ted_ sym_ swp clk_ alph a_ sel table e.2 microcontroller address map (cont.) m c_add m p_apr d7 d6 d5 d4 d3 d2 d1 do r/w by m c (sheet 4 of 5) L64724tm_300.book page 8 friday, april 14, 2000 2:17 pm
microcontroller address map e-9 group 4 (cont.) 183 55 adc_ bps ob_2c external control output bits, xctr[3:0] dem od_ rst fec_ rst r/w 184 56 reed-solomon max block count[7:0] 185 57 rsubc_threshold[7:0] 186 58 adc_ test_ en adc_ test_ start res. fifo_depth[4:0] 187 59 serial transmission start data, txsd[6:0] res. 188 60 serial transmission data, txd[7:0] 189 61 serial transmission end data, txed[7:0] 190 62 serial_ b serial_c[1:0] reserved serial _a 191 1. scratch pad registers reside physically within the m controller module. 2. lp_status[i] = 1 if loop control register lpi = 0. 3. acc_status[2 ]=1if m c accumulator < 0, acc_status[1 ]=1if m c accumulator >= 0, acc_status[0] = 1 if m c accumulator = 0. 4. this register is mapped from group 5 into m controller scratchpad memory space so as to be readable by the microcode. look at chapter 3 of the L64724 datasheet for more information. 5. the microcode assembler checks for accesses to unmapped addresses and writes to read-only addresses. it ?ags these instructions as illegal at assemble time. 6. this register resides physically within the m controller module. 7. registers 81-85 reside physically within the m controller module. table e.2 microcontroller address map (cont.) m c_add m p_apr d7 d6 d5 d4 d3 d2 d1 do r/w by m c (sheet 5 of 5) L64724tm_300.book page 9 friday, april 14, 2000 2:17 pm
e-10 L64724 on-chip microcontroller L64724tm_300.book page 10 friday, april 14, 2000 2:17 pm
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u.s. distributors by state a. e. avnet electronics http://www.hh.avnet.com b. m. bell microproducts, inc. (for habs) http://www.bellmicro.com i. e. insight electronics http://www.insight-electronics.com w. e. wyle electronics http://www.wyle.com alabama daphne i. e. tel: 334.626.6190 huntsville a. e. tel: 256.837.8700 b. m. tel: 256.705.3559 i. e. tel: 256.830.1222 w. e. tel: 800.964.9953 alaska a. e. tel: 800.332.8638 arizona phoenix a. e. tel: 480.736.7000 b. m. tel: 602.267.9551 w. e. tel: 800.528.4040 tempe i. e. tel: 480.829.1800 tucson a. e. tel: 520.742.0515 arkansas w. e. tel: 972.235.9953 california agoura hills b. m. tel: 818.865.0266 granite bay b. m. tel: 916.523.7047 irvine a. e. tel: 949.789.4100 b. m. tel: 949.470.2900 i. e. tel: 949.727.3291 w. e. tel: 800.626.9953 los angeles a. e. tel: 818.594.0404 w. e. tel: 800.288.9953 sacramento a. e. tel: 916.632.4500 w. e. tel: 800.627.9953 san diego a. e. tel: 858.385.7500 b. m. tel: 858.597.3010 i. e. tel: 800.677.6011 w. e. tel: 800.829.9953 san jose a. e. tel: 408.435.3500 b. m. tel: 408.436.0881 i. e. tel: 408.952.7000 santa clara w. e. tel: 800.866.9953 woodland hills a. e. tel: 818.594.0404 westlake village i. e. tel: 818.707.2101 colorado denver a. e. tel: 303.790.1662 b. m. tel: 303.846.3065 w. e. tel: 800.933.9953 englewood i. e. tel: 303.649.1800 idaho springs b. m. tel: 303.567.0703 connecticut cheshire a. e. tel: 203.271.5700 i. e. tel: 203.272.5843 wallingford w. e. tel: 800.605.9953 delaware north/south a. e. tel: 800.526.4812 tel: 800.638.5988 b. m. tel: 302.328.8968 w. e. tel: 856.439.9110 florida altamonte springs b. m. tel: 407.682.1199 i. e. tel: 407.834.6310 boca raton i. e. tel: 561.997.2540 bonita springs b. m. tel: 941.498.6011 clearwater i. e. tel: 727.524.8850 fort lauderdale a. e. tel: 954.484.5482 w. e. tel: 800.568.9953 miami b. m. tel: 305.477.6406 orlando a. e. tel: 407.657.3300 w. e. tel: 407.740.7450 tampa w. e. tel: 800.395.9953 st. petersburg a. e. tel: 727.507.5000 georgia atlanta a. e. tel: 770.623.4400 b. m. tel: 770.980.4922 w. e. tel: 800.876.9953 duluth i. e. tel: 678.584.0812 hawaii a. e. tel: 800.851.2282 idaho a. e. tel: 801.365.3800 w. e. tel: 801.974.9953 illinois north/south a. e. tel: 847.797.7300 tel: 314.291.5350 chicago b. m. tel: 847.413.8530 w. e. tel: 800.853.9953 schaumburg i. e. tel: 847.885.9700 indiana fort wayne i. e. tel: 219.436.4250 w. e. tel: 888.358.9953 indianapolis a. e. tel: 317.575.3500 iowa w. e. tel: 612.853.2280 cedar rapids a. e. tel: 319.393.0033 kansas w. e. tel: 303.457.9953 kansas city a. e. tel: 913.663.7900 lenexa i. e. tel: 913.492.0408 kentucky w. e. tel: 937.436.9953 central/northern/ western a. e. tel: 800.984.9503 tel: 800.767.0329 tel: 800.829.0146 louisiana w. e. tel: 713.854.9953 north/south a. e. tel: 800.231.0253 tel: 800.231.5775 maine a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 maryland baltimore a. e. tel: 410.720.3400 w. e. tel: 800.863.9953 columbia b. m. tel: 800.673.7461 i. e. tel: 410.381.3131 massachusetts boston a. e. tel: 978.532.9808 w. e. tel: 800.444.9953 burlington i. e. tel: 781.270.9400 marlborough b. m. tel: 800.673.7459 woburn b. m. tel: 800.552.4305 michigan brighton i. e. tel: 810.229.7710 detroit a. e. tel: 734.416.5800 w. e. tel: 888.318.9953 clarkston b. m. tel: 877.922.9363 minnesota champlin b. m. tel: 800.557.2566 eden prairie b. m. tel: 800.255.1469 minneapolis a. e. tel: 612.346.3000 w. e. tel: 800.860.9953 st. louis park i. e. tel: 612.525.9999 mississippi a. e. tel: 800.633.2918 w. e. tel: 256.830.1119 missouri w. e. tel: 630.620.0969 st. louis a. e. tel: 314.291.5350 i. e. tel: 314.872.2182 montana a. e. tel: 800.526.1741 w. e. tel: 801.974.9953 nebraska a. e. tel: 800.332.4375 w. e. tel: 303.457.9953 nevada las vegas a. e. tel: 800.528.8471 w. e. tel: 702.765.7117 new hampshire a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 new jersey north/south a. e. tel: 201.515.1641 tel: 609.222.6400 mt. laurel i. e. tel: 856.222.9566 pine brook b. m. tel: 973.244.9668 w. e. tel: 800.862.9953 parsippany i. e. tel: 973.299.4425 wayne w. e. tel: 973.237.9010 new mexico w. e. tel: 480.804.7000 albuquerque a. e. tel: 505.293.5119 L64724tm_300.book page 13 friday, april 14, 2000 2:17 pm
u.s. distributors by state (continued) new york hauppauge i. e. tel: 516.761.0960 long island a. e. tel: 516.434.7400 w. e. tel: 800.861.9953 rochester a. e. tel: 716.475.9130 i. e. tel: 716.242.7790 w. e. tel: 800.319.9953 smithtown b. m. tel: 800.543.2008 syracuse a. e. tel: 315.449.4927 north carolina raleigh a. e. tel: 919.859.9159 i. e. tel: 919.873.9922 w. e. tel: 800.560.9953 north dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 ohio cleveland a. e. tel: 216.498.1100 w. e. tel: 800.763.9953 dayton a. e. tel: 614.888.3313 i. e. tel: 937.253.7501 w. e. tel: 800.575.9953 strongsville b. m. tel: 440.238.0404 valley view i. e. tel: 216.520.4333 oklahoma w. e. tel: 972.235.9953 tulsa a. e. tel: 918.459.6000 i. e. tel: 918.665.4664 oregon beaverton b. m. tel: 503.524.1075 i. e. tel: 503.644.3300 portland a. e. tel: 503.526.6200 w. e. tel: 800.879.9953 pennsylvania mercer i. e. tel: 412.662.2707 philadelphia a. e. tel: 800.526.4812 b. m. tel: 877.351.2355 w. e. tel: 800.871.9953 pittsburgh a. e. tel: 412.281.4150 w. e. tel: 440.248.9996 rhode island a. e. 800.272.9255 w. e. tel: 781.271.9953 south carolina a. e. tel: 919.872.0712 w. e. tel: 919.469.1502 south dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 tennessee w. e. tel: 256.830.1119 east/west a. e. tel: 800.241.8182 tel: 800.633.2918 texas arlington b. m. tel: 817.417.5993 austin a. e. tel: 512.219.3700 b. m. tel: 512.258.0725 i. e. tel: 512.719.3090 w. e. tel: 800.365.9953 dallas a. e. tel: 214.553.4300 b. m. tel: 972.783.4191 w. e. tel: 800.955.9953 el paso a. e. tel: 800.526.9238 houston a. e. tel: 713.781.6100 b. m. tel: 713.917.0663 w. e. tel: 800.888.9953 richardson i. e. tel: 972.783.0800 rio grande valley a. e. tel: 210.412.2047 stafford i. e. tel: 281.277.8200 utah centerville b. m. tel: 801.295.3900 murray i. e. tel: 801.288.9001 salt lake city a. e. tel: 801.365.3800 w. e. tel: 800.477.9953 vermont a. e. tel: 800.272.9255 w. e. tel: 716.334.5970 virginia a. e. tel: 800.638.5988 w. e. tel: 301.604.8488 haymarket b. m. tel: 703.754.3399 spring?eld b. m. tel: 703.644.9045 washington kirkland i. e. tel: 425.820.8100 maple valley b. m. tel: 206.223.0080 seattle a. e. tel: 425.882.7000 w. e. tel: 800.248.9953 west virginia a. e. tel: 800.638.5988 wisconsin milwaukee a. e. tel: 414.513.1500 w. e. tel: 800.867.9953 wauwatosa i. e. tel: 414.258.5338 wyoming a. e. tel: 800.332.9326 w. e. tel: 801.974.9953 L64724tm_300.book page 14 friday, april 14, 2000 2:17 pm
sales of?ces and design resource centers lsi logic corporation corporate headquarters 1551 mccarthy blvd milpitas ca 95035 tel: 408.433.8000 fax: 408.433.8989 north america california irvine 18301 von karman ave suite 900 irvine, ca 92612 tel: 949.809.4600 fax: 949.809.4444 pleasanton design center 5050 hopyard road, 3rd floor suite 300 pleasanton, ca 94588 tel: 925.730.8800 fax: 925.730.8700 san diego 7585 ronson road suite 100 san diego, ca 92111 tel: 858.467.6981 fax: 858.496.0548 silicon valley 1551 mccarthy blvd sales of?ce m/s c-500 milpitas, ca 95035 tel: 408.433.8000 fax: 408.954.3353 design center m/s c-410 tel: 408.433.8000 fax: 408.433.7695 wireless design center 11452 el camino real suite 210 san diego, ca 92130 tel: 858.350.5560 fax: 858.350.0171 colorado boulder 4940 pearl east circle suite 201 boulder, co 80301 tel: 303.447.3800 fax: 303.541.0641 colorado springs 4420 arrowswest drive colorado springs, co 80907 tel: 719.533.7000 fax: 719.533.7020 fort collins 2001 dan?eld court fort collins, co 80525 tel: 970.223.5100 fax: 970.206.5549 florida boca raton 2255 glades road suite 324a boca raton, fl 33431 tel: 561.989.3236 fax: 561.989.3237 georgia alpharetta 2475 north winds parkway suite 200 alpharetta, ga 30004 tel: 770.753.6146 fax: 770.753.6147 illinois oakbrook terrace two mid american plaza suite 800 oakbrook terrace, il 60181 tel: 630.954.2234 fax: 630.954.2235 kentucky bowling green 1262 chestnut street bowling green, ky 42101 tel: 270.793.0010 fax: 270.793.0040 maryland bethesda 6903 rockledge drive suite 230 bethesda, md 20817 tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham 200 west street waltham, ma 02451 tel: 781.890.0180 fax: 781.890.6158 burlington - mint technology 77 south bedford street burlington, ma 01803 tel: 781.685.3800 fax: 781.685.3801 minnesota minneapolis 8300 norman center drive suite 730 minneapolis, mn 55437 tel: 612.921.8300 fax: 612.921.8399 new jersey red bank 125 half mile road suite 200 red bank, nj 07701 tel: 732.933.2656 fax: 732.933.2643 cherry hill - mint technology 215 longstone drive cherry hill, nj 08003 tel: 856.489.5530 fax: 856.489.5531 new york fairport 550 willowbrook of?ce park fairport, ny 14450 tel: 716.218.0020 fax: 716.218.9010 north carolina raleigh phase ii 4601 six forks road suite 528 raleigh, nc 27609 tel: 919.785.4520 fax: 919.783.8909 oregon beaverton 15455 nw greenbrier parkway suite 235 beaverton, or 97006 tel: 503.645.0589 fax: 503.645.6612 texas austin 9020 capital of tx highway north building 1 suite 150 austin, tx 78759 tel: 512.388.7294 fax: 512.388.4171 plano 500 north central expressway suite 440 plano, tx 75074 tel: 972.244.5000 fax: 972.244.5001 houston 20405 state highway 249 suite 450 houston, tx 77070 tel: 281.379.7800 fax: 281.379.7818 canada ontario ottawa 260 hearst way suite 400 kanata, on k2l 3h1 tel: 613.592.1263 fax: 613.592.3253 international france paris lsi logic s.a. immeuble europa 53 bis avenue de l'europe b.p. 139 78148 velizy-villacoublay cedex, paris tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany munich lsi logic gmbh orleansstrasse 4 81669 munich tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart mittlerer pfad 4 d-70499 stuttgart tel: 49.711.13.96.90 fax: 49.711.86.61.428 italy milan lsi logic s.p.a. centro direzionale colleoni palazzo orione ingresso 1 20041 agrate brianza, milano tel: 39.039.687371 fax: 39.039.6057867 japan tokyo lsi logic k.k. rivage-shinagawa bldg. 14f 4-1-8 kounan minato-ku, tokyo 108-0075 tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka crystal tower 14f 1-2-27 shiromi chuo-ku, osaka 540-6014 tel: 81.6.947.5281 fax: 81.6.947.5287 L64724tm_300.book page 15 friday, april 14, 2000 2:17 pm
sales of?ces and design resource centers (continued) korea seoul lsi logic corporation of korea ltd 10th fl., haesung 1 bldg. 942, daechi-dong, kangnam-ku, seoul, 135-283 tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands eindhoven lsi logic europe ltd world trade center eindhoven building rijder bogert 26 5612 lz eindhoven tel: 31.40.265.3580 fax: 31.40.296.2109 singapore singapore lsi logic pte ltd 7 temasek boulevard #28-02 suntec tower one singapore 038987 tel: 65.334.9061 fax: 65.334.4749 sweden stockholm lsi logic ab finlandsgatan 14 164 74 kista tel: 46.8.444.15.00 fax: 46.8.750.66.47 taiwan taipei lsi logic asia, inc. taiwan branch 10/f 156 min sheng e. road section 3 taipei, taiwan r.o.c. tel: 886.2.2718.7828 fax: 886.2.2718.8869 united kingdom bracknell lsi logic europe ltd greenwood house london road bracknell, berkshire rg12 2ub tel: 44.1344.426544 fax: 44.1344.481039 sales of?ces with design resource centers L64724tm_300.book page 16 friday, april 14, 2000 2:17 pm
international distributors australia new south wales reptechnic pty ltd 3/36 bydown street neutral bay, nsw 2089 tel: 612.9953.9844 fax: 612.9953.9683 belgium acal nv/sa lozenberg 4 1932 zaventem tel: 32.2.7205983 fax: 32.2.7251014 china beijing lsi logic international services inc. beijing representative of?ce room 708 canway building 66 nan li shi lu xicheng district beijing 100045, china tel: 86.10.6804.2534 to 38 fax: 86.10.6804.2521 france rungis cedex azzurri technology france 22 rue saarinen sillic 274 94578 rungis cedex tel: 33.1.41806310 fax: 33.1.41730340 germany haar ebv elektronik hans-pinsel str. 4 d-85540 haar tel: 49.89.4600980 fax: 49.89.46009840 munich avnet emg gmbh stahlgruberring 12 81829 munich tel: 49.89.45110102 fax: 49.89.42.27.75 wuennenberg-haaren peacock ag graf-zepplin-str 14 d-33181 wuennenberg-haaren tel: 49.2957.79.1692 fax: 49.2957.79.9341 hong kong hong kong avt industrial ltd unit 608 tower 1 cheung sha wan plaza 833 cheung sha wan road kowloon, hong kong tel: 852.2428.0008 fax: 852.2401.2105 serial system (hk) ltd 2301 nanyang plaza 57 hung to road, kwun tong kowloon, hong kong tel: 852.2995.7538 fax: 852.2950.0386 india bangalore spike technologies india private ltd 951, vijayalakshmi complex, 2nd floor, 24th main, j p nagar ii phase, bangalore, india 560078 tel: 91.80.664.5530 fax: 91.80.664.9748 israel tel aviv eastronics ltd 11 rozanis street p.o. box 39300 tel aviv 61392 tel: 972.3.6458777 fax: 972.3.6458666 japan tokyo daito electron sogo kojimachi no.3 bldg 1-6 kojimachi chiyoda-ku, tokyo 102-8730 tel: 81.3.3264.0326 fax: 81.3.3261.3984 global electronics corporation nichibei time24 bldg. 35 tansu-cho shinjuku-ku, tokyo 162-0833 tel: 81.3.3260.1411 fax: 81.3.3260.7100 technical center tel: 81.471.43.8200 marubeni solutions 1-26-20 higashi shibuya-ku, tokyo 150-0001 tel: 81.3.5778.8662 fax: 81.3.5778.8669 shinki electronics myuru daikanyama 3f 3-7-3 ebisu minami shibuya-ku, tokyo 150-0022 tel: 81.3.3760.3110 fax: 81.3.3760.3101 yokohama-city innotech 2-15-10 shin yokohama kohoku-ku yokohama-city, 222-8580 tel: 81.45.474.9037 fax: 81.45.474.9065 macnica corporation hakusan high-tech park 1-22-2 hadusan, midori-ku, yokohama-city, 226-8505 tel: 81.45.939.6140 fax: 81.45.939.6141 the netherlands eindhoven acal nederland b.v. beatrix de rijkweg 8 5657 eg eindhoven tel: 31.40.2.502602 fax: 31.40.2.510255 switzerland brugg lsi logic sulzer ag mattenstrasse 6a ch 2555 brugg tel: 41.32.3743232 fax: 41.32.3743233 taiwan taipei avnet-mercuries corporation, ltd 14f, no. 145, sec. 2, chien kuo n. road taipei, taiwan, r.o.c. tel: 886.2.2516.7303 fax: 886.2.2505.7391 lumax international corporation, ltd 7th fl., 52, sec. 3 nan-kang road taipei, taiwan, r.o.c. tel: 886.2.2788.3656 fax: 886.2.2788.3568 prospect technology corporation, ltd 4fl., no. 34, chu luen street taipei, taiwan, r.o.c. tel: 886.2.2721.9533 fax: 886.2.2773.3756 wintech microeletronics co., ltd 7f., no. 34, sec. 3, pateh road taipei, taiwan, r.o.c. tel: 886.2.2579.5858 fax: 886.2.2570.3123 united kingdom maidenhead azzurri technology ltd 16 grove park business estate waltham road white waltham maidenhead, berkshire sl6 3lw tel: 44.1628.826826 fax: 44.1628.829730 milton keynes ingram micro (uk) ltd garamonde drive wymbush milton keynes buckinghamshire mk8 8df tel: 44.1908.260422 swindon ebv elektronik 12 interface business park bincknoll lane wootton bassett, swindon, wiltshire sn4 8sy tel: 44.1793.849933 fax: 44.1793.859555 sales of?ces with design resource centers L64724tm_300.book page 17 friday, april 14, 2000 2:17 pm
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